Logic Circuits; Regulator Circuits - Icom IC-718 Service Manual

4-3-3 REFERENCE OSCILLATOR CIRCUIT
(PLL UNIT)
The reference oscillator circuit consists of Q9 and X1. A
32.00 MHz reference frequency is oscillated to produce a
2nd LO signal, DDS reference frequency and BFO DDS
clock signal.
The 32.00 MHz reference frequency is doubled at Q10 to
obtain the 2nd LO signal. The resulting 64.00 MHz signal is
filtered at the bandpass filter and is then applied to the MAIN
unit via J1 as the 2nd LO signal.

4-4 LOGIC CIRCUITS

4-4-1 BAND SELECTION DATA (MAIN UNIT)
To selection the correct bandpass filter and low-pass filter,
the CPU outputs the following band selection data from the
I/O expander (MAIN unit; IC3001) depending on the dis-
played frequency.
• Band selection data
Band
0.03–1.59999 MHz
1.6–1.99999 MHz
2.0–3.99999 MHz
4.0–7.99999 MHz
8.0–10.99999 MHz
11.0–14.99999 MHz
15.0–21.99999 MHz
22.0–30.00000 MHz
• FREQUENCY CONSTRUCTION
ANT
1st mixer
Q1101–Q1104
1st LO
64.485–
97.455 MHz
BPF
Q18
Loop
filter
DDS
IC6
Band
BPF LPF
voltage
B0
7.4 V
B1
B2 6.0 V
B3 5.0 V
B4 0 V
B5 4.0 V
B6 3.1 V
B7 2.2V
64.455 MHz
Crystal
filter
Reference
oscillator
X1: 32.0 MHz
4-4-2 RIT CONTROL (FRONT UNIT)
The [RIT] control shifts the "RIV" voltage in order to shift the
receive frequency. The voltage is applied to the A/D con-
verter section of the CPU (IC1, pin 1). The CPU shifts the N-
data for the DDS IC.
4-4-3 CPU (LOGIC UNIT)
The CPU (IC1) contains an 8-bit CMOS CPU, a 60 k-byte
ROM, a 2 k-byte RAM. A 9.8304 MHz clock is used for rapid
operation. The CPU controls the operating frequency, mode,
function display, etc. The memory channel information is
stored in the EEPROM (IC2).
The Icom CI-V network system allows the IC-718 to be
remotely controlled by a personal computer using an RS-
232C I/O port.

4-5 REGULATOR CIRCUITS

Either +8 V, +5 V or –5 V DC is supplied from a corre-
sponding regulator circuit. +8 V, +5 V and –5 V DC are reg-
ulated at the following circuits using 13.8 V DC.
(1) +5 V REGULATOR (FRONT UNIT)
L1
+ 5 V DC is provided by a three-terminal voltage regulator
(IC4).
L2
L3 (2) + 8 V REGULATOR (MAIN UNIT)
+ 8 V DC is provided by a three-terminal voltage regulator
L4 (IC17).
L5
(3) –5 V REGULATOR (MAIN UNIT)
IC16 generates a negative pulse-type voltage by converting
L6
the DC input to AC voltage (approx. 6.7 kHz) as a multi-
vibrator. The voltage is rectified at D80 and D81, regulated
by a Zener diode (D82) and C249, and is then applied to the
MAIN and PLL units.
MAIN unit
2nd mixer
D401 455 kHz
2nd LO
64.0 MHz
BPF
PLL unit
2
Q10
Q9
4 - 6
Demodulator
BPF
BFO
453.3–
456.5 kHz
LPF
DDS
to AF circuit
IC2