Logic Circuits - Icom IC-725 Service Manual

PLL CIRCUIT
BLOCK DIAGRAM
Nt
MAIN
LOOP
VC01
Q12-Q14
LOOP
FILTER
0/\vcoi
\
^Jq17
fv:
70.951
5~
100.4515
MHz
/^
^VC03
V
^yoi9
AMP
Q23
fv
-r-
LO
AMP
Q24
.
1
St
LO
to
'main
unit
1013
N
PLL
^
t/
1C
1014
V0O4
021
L-f,o: 8.5015-37.88951
MHz
DIVIDER
1/4
BUFFER
026
LPF
1016
AMP
027
15.36
MHz
r
—
1015
DIVIDER
1/2
DDS
fF
DATA
LOOP
FILTER
V005
0.61-1.12199
MHz
BUFFER
032
LPF
1017
BUFFER
034
SUB LOOP
REFERENOE
OSOILLATOR
X2
HD
30.72
MHz
033
MULTIPLIER
x2
036
f,o:
62.05-
62.56199
MHz
2nd
LO
61.44
MHz
777
Fig.
6
4-4
LOGIC CIRCUITS
4-4-1
BAND SELECTION DATA
(PLL UNIT)
To
select
the correct
bandpass
filter,
the low-pass
filter
and
VCOs
on
the
MAIN and PLL UNITS,
the
CPU
outputs the
following data.
R29~R40
and
D29~D35
convert the
"B0"~"B7"
signals
into
a
band
voltage
(0—7.5
V) for
external
equipment.
FREQUENOY
(MHz)
BPF
BAND
VOLTAGE
LPF
VCO
0.5—1.599
BO
7.5
V
LI
VC01
1.6-1.999 B1
2.0—3.999
B2
5.9
V
L2
4.0-7.999
B3
5.0
V
L3
8.0—10.999 B4 0.0
V
L4
VC02
11.0-14.999
B5
4.1
V
15.0—21.999 B6
3.2
V
L5
VC03
22.0-30.0
B7
2.2
V
L6
VC04