Sel Events Supported By The Mpcbl0001 Sbc - Intel NetStructure MPCBL0001 Technical Product Specification

Table 3. SEL Events Supported by the MPCBL0001 SBC (Sheet 1 of 4)
Sensor Sensor
Type Type Code
Reserved 00h
Temperature 01h
Voltage 02h
Processor 07h
Power Unit 01h
Memory 0Ch
NOTE:
1. These sensor offsets do not generate events, but they are valid offsets when reading the sensor values.
2. Watchdog sensor refers to WDT#1 per
Technical Product Specification
Order #273817
®
Intel NetStructure MPCBL0001 High Performance Single Board Computer
Sensor-Specific
Offset (Event
Data 1, Bit 0-3)
- Reserved
- Temperature
- Voltage
00h IERR
01h Thermal Trip
04h FRB3/Processor Startup/
Initialization Failure
(CPU did not start)
05h Configuration Error
07h Processor Presence
1
Detected
09h Terminator Presence
1
Detected
00h Power Off/Power On
05h Soft Power Control
Failure (unit did not
respond to request to
turn on)
00h Correctable ECC
01h Uncorrectable ECC
Section 3.13.1.
Event
-
Threshold exceeded for upper critical, upper non-
critical, lower critical and lower non-critical
thresholds. Refer to
IPMC Firmware 1.0" on page 37
thresholds data.
Voltage exceeded upper critical, upper non-critical,
lower critical and lower non-critical thresholds. Refer
to Table 4 for sensor thresholds data.
Processor IERR has occurred.
Processor thermal trip has occurred.
An FRB3 Timer (30 seconds) was implemented to
detect the failure of the CPUs from booting.
Event data 3 = Last Post 80 code byte
CPU 0 and CPU 1 are not present.
Normal power off indication. Offset 0 is just a status
indicating that the payload power is off. It does not
generate an event when it is set. (For internal use).
The Power Unit sensor is used to detect when the
Payload power does not come up when the board is
told to power on.
When the board enters M4 state, the IPMC asserts a
Power Enable line to cause the Payload to power up.
The IPMC then waits for another line that indicates
that the power has come up successfully. If that line
does not assert within 2 seconds, then offset 05h is
asserted on the Power Unit sensor, which generates
an event to notify the Shelf Manager of the failure.
Event data 3 = DIMM pair number
00 refers to J8/J9
01 refers to J10/J11
Event data 3 = DIMM pair number
00 refers to J8/J9
01 refers to J10/J11
Contents
Remarks
Table 4, "Sensor Thresholds for
for sensor
33