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Intel NetStructure
MPCBL0001 High Performance Single Board Computer
Contents
3.13
Watchdog Timers (WDTs)
Figure 10, "Watchdog Timers" on page 64
timers (WDTs) on the MPCBL0001 SBC.
Figure 10.
Watchdog Timers
(South Bridge)
3.13.1
WDT #1
The first WDT (WDT #1) is a hardware timer in the IPMC. WDT #1 is IPMI compliant; its
interaction with the host processor BIOS or system software is accomplished through IPMI
commands over the Keyboard Controller Style (KCS) interface to the IPMC. The host processor
uses the Set Watchdog Timer message to configure WDT #1, then the Reset Watchdog Timer
message to strobe the timer.
WDT #1 can be set to any value between 100 ms and 6,553,600 ms in 100 ms intervals. Another
configuration parameter is an indicator of which software is controlling WDT #1. This has five
state settings:
1. BIOS FRB2: Used during fault-resilient booting to detect issues in the BIOS.
2. BIOS/POST: Used while the BIOS is running through its POST operations.
3. OS Load: Set by the BIOS just before an OS load, then reset by the OS (the OS must be
enabled to do so) when it finishes booting.
4. SMS/OS: Used by the system management software or the OS.
5. OEM: Used by any OEM software.
64
ICH3
Strobe
WDT #3
Isolation Logic
shows the relationship between the three watchdog
Host
Processor(s)
Strobe
IPMC
WDT #1
IPMB-A
IPMB-B
Isolation Logic
Strobe
PLD
WDT #2
B1368-02
Technical Product Specification
Order #273817
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