Analog Devices MicroConverter ADuC824 Quick Reference Manual page 2

DATA MEMORY: RAM, SFRs, user Flash/EE (all read/write)
LOWER RAM
127 7Fh
General Purpose
... ...
Area
(bit addresses)
48 30h
47
2Fh 7Fh 7Eh 7Dh 7Ch
46 2Eh 77h 76h 75h 74h
45 2Dh 6Fh 6Eh 6Dh 6Ch
44 2Ch 67h 66h 65h 64h
43 2Bh 5Fh 5Eh 5Dh 5Ch
42 2Ah 57h 56h 55h 54h
41 29h Bit Addressable 4Fh 4Eh 4Dh 4Ch
Area
40 28h 47h 46h 45h 44h
39 27h 3Fh 3Eh 3Dh 3Ch
38 26h 37h 36h 35h 34h
37 25h 2Fh 2Eh 2Dh 2Ch
36 24h 27h 26h 25h 24h
35 23h 1Fh 1Eh 1Dh 1Ch
34 22h 17h 16h 15h 14h
33 21h 0Fh 0Eh 0Dh 0Ch
32 20h 07h 06h 05h 04h
31 1Fh R7
30 1Eh R6
29 1Dh R5
DATA MEMORY SPACE
28 1Ch R4 Register
Bank 3 (read/write area)
27 1Bh R3
26 1Ah R2
25 19h R1
24 18h R0 9Fh ( page 159 )
23 17h R7
22 16h R6
640 bytes
21 15h R5
(160 pages)
20 14h R4 Register
data
Bank 2
Flash/EE
19 13h R3
(accessible
18 12h R2 through
SFRs)
17 11h R1
16 10h R0
15 0Fh R7 00h ( page 0 )
14 0Eh R6
13 0Dh R5
12 0Ch R4 Register
FFh
Bank 1
128 bytes
11 0Bh R3
upper RAM
10 0Ah R2
(indirect
addressing
addressing
9 09h R1
only)
8
08h R0
128 bytes
7 07h R7
lower RAM
6 06h R6
(direct or
indirect
5 05h R5
addressing)
00h
4 04h R4 Register
Bank 0
3
03h R3
2 02h R2
1 01h R1
0 00h R0
lower RAM
details
7Bh 7Ah 79h 78h
73h 72h 71h 70h
6Bh 6Ah 69h 68h
63h 62h 61h 60h
5Bh 5Ah 59h 58h
53h 52h 51h 50h
4Bh 4Ah 49h 48h
43h 42h 41h 40h
3Bh 3Ah 39h 38h
33h 32h 31h 30h
2Bh 2Ah 29h 28h
23h 22g 21h 20h
1Bh 1Ah 19h 18h
13h 12h 11g 10h
0Bh 0Ah 09h 08h
03h 02h 01h 00h
FFFFFFh
external
data
memory
(16MEG
addressable)
SFRs
(direct
only)
000000h
mnemonic
SFR details
reset value
*
calibration coefficients are preconfigured at power-up to factory calibrated values
SFR MAP & RESET VALUES
these bits are contained in this byte
mnemonic
SPR1 SPR0 SPICON
address reset value
F9h 0 F8h 0 F8h 00h
address
SFR DESCRIPTIONS
ADCSTAT PSMCON
ADC Status Register
RDY0 primary ADC ready flag PSMCON.7 DV
RDY1 auxiliary ADC ready flag PSMCON.6 AV
CAL calibration flag PSMCON.5 PSM interrupt bit
NOXREF no external reference flag PSMCON.4 DV
ERR0 primary ADC error flag PSMCON.3
ERR1 auxiliary ADC error flag PSMCON.2 AV
PSMCON.1
ADCMODE
ADC Mode Register
PSMCON.0 PSM powerdown control (1=on / 0=off)
ADMODE.5 primary ADC enable bit
SP
ADMODE.4 auxiliary ADC enable bit
ADMODE.2 mode bits
IE
Interrupt Enable register #1
ADMODE.1 [powerdown, idle, sngl-conv, cont-conv,
ADMODE.0 zero-selfcal, fs-selfcal, zero-syscal, fs-syscal]
EA enable inturrupts (0=all inturrupts disabled)
ADC0CON EADC enable RDY0/RDY1 (ADC interrupt)
Primary ADC Control Register
ET2 enable TF2/EXF2 (Timer2 overflow interrupt)
AD0CON.7 (this bit must contain zero)
ES enable RI/TI (serial port interrupt)
AD0CON.6 external reference select bit (0=internal ref)
ET1 enable TF1 (Timer1 overflow interrupt)
AD0CON.5 channel selection bits:
EX1 enable IE1 (external interrupt 1)
AD0CON.4 [AIN1-AIN2,AIN3-AIN4,AIN2-AIN2,AIN3-AIN2]
ET0 enable TF0 (Timer0 overflow interrupt)
AD0CON.3 unipolar select bit (0=bipolar)
EX0 enable IE0 (external interrupt 0)
AD0CON.2 range select bits:
IEIP2
Interrupt Enable/Priority register #2
AD0CON.1 [±20mV, ±40mV, ±80mV, ±160mV, ±320mV,
AD0CON.0 ±640mV, ±1.28V, ±2.56V]
IEIP2.7 (not used)
ADC1CON IEIP2.6 pirority of TII interrupt (timer interval)
Auxiliary ADC Control Register
IEIP2.5 priority of PSMI interrupt (power supply monitor)
AD1CON.6 external reference select bit (0=internal ref)
IEIP2.4 priority of ISPI interrupt (serial interface)
AD1CON.5 channel selection bits:
IEIP2.3 (this bit must contain zero)
AD1CON.4 [AIN3, AIN4, TEMP, AIN5]
IEIP2.2 enable TII interrupt (timer interval)
AD1CON.3 unipolar select bit (0 = bipolar)
IEIP2.1 enable PSMI interrupt (power supply monitor)
SF IEIP2.0 enable ISPI interrupt (serial interface)
Sync Filter Register: f = 4,096Hz ÷ (3·SF)
ADC
IP
Interrupt Priority register
OF0H,OF0M,OF0L
ADC0 offset coefficient
IP.7 (not used)
PADC priority of RDY0/RDY1 (ADC interrupt)
OF1H,OF1L
ADC1 offset coefficient
PT2 priority of TF2/EXF2 (Timer2 overflow interrupt)
PS priority of RI/TI (serial port interrupt)
GN0H,GN0M,GN0L
ADC0 gain coefficient
PT1 priority of TF1 (Timer1 overflow interrupt)
PX1 priority of IE1 (external INT1)
GN1H,GN1L
ADC1 gain coefficient PT0 priority of TF0 (Timer0 overflow interrupt)
PX0 priority of IE0 (external INT0)
ADC0H,ADC0M,ADC0L ADC0 data TMOD Timer Mode register
TMOD.3/.7 gate control bit (0=ignore INTx)
ADC1H,ADC1L ADC1 data
TMOD.2/.6 counter/timer select bit (0=timer)
TMOD.1/.5 timer mode selecton bits
ICON
Current Source Control Register TMOD.0/.4
(upper nibble = Timer1, lower nibble = Timer0)
ICON.6 burnout current enable bit
ICON.5 ADC1 current correction bit (0=correction off) TCON
Timer Control register
ICON.4 ADC0 current correction bit (0=correction off)
TF1 Timer1 overflow flag
ICON.3 I2 pin select bit [0=pin4 / 1=pin3]
TR1 Timer1 run control (0=off, 1=run)
ICON.2 I1 pin select bit [0=pin3 / 1=pin4]
TF0 Timer0 overflow flag
ICON.1 I2 enable bit (0=disable)
TR0 Timer0 run control (0=off, 1=run)
ICON.0 I1 enable bit (0=disable)
IE1 external INT1 flag
DACCON
DAC Control register
IT1 IE1 type (0=level trig, 1=edge trig)
IE0 external INT0 flag
DACCON.4 DAC pin select bit [0=pin3 / 1=pin12]
IT0 IE0 type (0=level trig, 1=edge trig)
DACCON.3 ModeSelect (0=12bit, 1=8bit)
DACCON.2 RangeSelect (0=2.5V, 1=AV ) TH0,TL0
DD
DACCON.1 Clear DAC (0=0V, 1=normal operation)
DACCON.0 PowerDown DAC (0=off, 1=on)
TH1,TL1
DACH,DACL
DAC data registers
T2CON
PLLCON
PLL Control Register
TF2 overflow flag
PLLCON.7 oscillator powerdown control bit (0=normal) EXF2 external flag
PLLCON.6 PLL lock indicator flag (0=out of lock) RCLK receive clock enable (0=Timer1 used for RxD clk)
PLLCON.5 (this bit must contain zero) TCLK transmit clock enable (0=Timer1 used for TxD clk)
PLLCON.4 EA detect status bit (reflects state of EA pin) EXEN2 external enable (0=ignore T2EX, 1=cap/rld on T2EX)
PLLCON.3 "fast interrupt" control bit (0=normal) TR2 run control (0=stop, 1=run)
PLLCON.2 3-bit clock divideer value, "CD" (default=3): CNT2 timer/counter select (0=timer, 1=counter)
PLLCON.1 CAP2 capture/reload select (0=reload, 1=capture)
CD
f = 12,582,912Hz ÷ 2
CORE
PLLCON.0
TH2,TL2
TIMECON
Time Interval Counter Control Register
RCAP2H,RCAP2L
TIMECON.6 24hour select bit (0=255hour)
TIMECON.5 interval timebase select bits
P0
TIMECON.4 [128th sec, seconds, minutes, hours] Port0 register
TIMECON.3 single time interval control bit (0=reload&restart)
TIMECON.2 time interval interrupt bit, "TII" P1
Port1 register
TIMECON.1 time interval enable bit (0=disable&clear)
P1.2-1.7 analog/digital pins (1=analog function, 0=digital input)
TIMECON.0 time clock enable bit (0=disable)
T2EX timer/counter 2 capture/reload trigger (or digital I/O)
INTVAL
TIC Interval Register T2 timer/counter 2 external input (or digital I/O)
P2
Port2 register
HTHSEC
TIC Elapsed 128th Second Register
P3
Port3 register
SEC TIC Elapsed Seconds Register
RD external data memory read strobe
MIN
TIC Elapsed Minutes Register
WR external data memory write strobe
HOUR T1 timer/counter 1 external input
TIC Elapsed Hours Register
T0 timer/counter 0 external input
CHIPID INT1 external interrupt 1
Chip ID Register (0X hex = ADuC824)
INT0 external interrupt 0
TxD serial port transmit data line
ECON
Data Flash/EE comand register
RxD serial port receive data line
01h READ page 81h READ byte
SCON Serial communications Control register
02h PROGRAM page 82h PROGRAM byte
04h VERIFY page 0Fh EXIT ULOAD mode SM0 UART mode control bits
05h ERASE page F0h ENTER ULOAD mode SM1 00 - 8bit shift register - F
06h ERASE ALL (all others reserved) 01 - 8bit UART
10 - 9bit UART
EADRH,EADRL
Data Flash/EE address registers
11 - 9bit UART
SM2 in modes 2&3, enables multiprocessor communication
EDATA1,EDATA2,EDATA3,EDATA4
REN receive enable control bit
TB8 in modes 2&3, 9th bit transmitted
Data Flash/EE data registers
RB8 in modes 2&3, 9th bit received
TI transmit interrupt flag
SPICON SPI Control register
RI receive interrupt flag
ISPI SPI inturrupt (set at end of SPI transfer)
SBUF
Serial port Buffer register
WCOL write collision error flag
SPE SPI enable (0=DCON enable, 1=SPI enable)
PCON
Power Control register
SPIM master mode select (0=slave)
CPOL clock polarity select (0=SCLK idles low)
PCON.7 double baud rate control
CPHA clock phase select (0=leading edge latch)
PCON.6 enable serial interrupt (ISI) from power-down mode
SPR1 SPI bitrate select bits
PCON.5 enable interrupt 0 (INT0) from power-down mode
SPR0 bitrate = F / [2, 4, 8, 16]
CORE PCON.4 ALE disable (0=normal, 1=forces ALE high)
SPIDAT PCON.3 general purpose flag
SPI Data register
PCON.2 general purpose flag
PCON.1 power-down control bit (0=normal)
DCON
D0 & D1 Control register
PCON.0 idle-mode control (0=normal)
(enabled if SPE=0, see SPICON register above)
PSW Program Status Word
D1 D1 output bit
D1EN D1 output enable (0=disable) CY carry flag
D0 D0 output bit AC auxiliary carry flag
D0EN D0 output enable (0=disable) F0 general purpose flag 0
RS1 register bank select control bits
WDCON
Watchdog Timer control register
RS0 active register bank = [0,1,2,3]
PRE3 watchdog timeout selection bits OV overflow flag
PRE2 0000-0111 = timeout=[15.6, 31.2, 62.5, 125, 500 F1 general purpose flag 1
PRE1 1000 = immediate reset 1000, 2000] ms P parity of ACC
PRE0 all others codes = reserved
DPP
WDIR watchdog interrupt response enable
WDS watchdog status flag
DPH,DPL (DPTR)
WDE watchdog enable
WDWR watchdog write enable
ACC
Accumulator
B
auxiliary math register
Power Supply Monitor control register
compare bit (0=fault)
DD
compare bit (0=fault)
DD
trip point select bits
DD
[4.63V, 3.08V, 2.93V, 2.63V]
trip point select bits
DD
[4.63V, 3.08V, 2.93V, 2.63V]
Stack Pointer
[13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]
Timer0 registers
Timer1 registers
Timer2 Control register
Timer2 register
Timer2 Reload/Capture
baud rate:
/12
CORE
- TimerOverflowRate/32(x2)
- F /64(x2)
CORE
- TimerOverflowRate/32(x2)
Data Pointer Page
Data Pointer