SOLTEK SL-75MIV User Manual page 64

75MIV
DRAM Timing by SPD This item allows you to select DRAM Timing by SPD
DRAM Clock This item allows you to control the DRAM speed.
SDRAM Cycle Length
Bank Interleave The choice: Disabled, 2 Bank, 4 Bank.
DRAM Drive Strength Leave this item with Auto mode.
DRAM Drive Value When "DRAM Drive Strength" is set to "Auto", this
Memory Hole In order to improve performance, certain space in
PCI Master Pipeline
P2C/C2P Concurrency This item allows you to enable/disable the PCI to CPU,
Fast R-W Turn Around This item controls the DRAM timing. It allows you to
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or not.
SPD (Serial Presence Detect) you can find it located
on your memory modules, BIOS reads information
coded in SPD during system boot up resulting in a
accurate memory operation.
The choice: Host Clock, HCLK+33M.
You can select CAS latency time in HCLKs of 2 or 3.
Time The system board designer should have set the val-
ues in this field, depending on the DRAM installed.
Do not change the values in this field unless you
change specifications of the installed DRAM or the
installed CPU.
The choice: Auto, Manual.
item will be unable to be selected. We don't recom-
mend user to adjust this item.
memory is reserved for ISA cards. This memory must
be mapped into the memory space below 16MB.
The choice: 15M-16M, Disabled.
Use default setting.
Req
CPU to PCI concurrency.
The choice: Enabled, Disabled.
enable / disable the fast read / write turn around.
The choice: Enabled, Disabled.