Furuno CI-68 Installation Manual page 45

0 V
Keying pulse needed
If the level is out of the ratings or KP output circuit is not provided, take the measures
shown on the next two pages to prevent equipment malfunction.
Buffer circuit for positive-going KP
KP out
Interfering Interfering
Equipment Equipment
Buffer circuit for negative-going KP
KP out
Interfering Interfering
Equipment Equipment
The following method also is available.
Additional Circuit Additional Circuit
Buffer circuit for keying pulse (KP)
DIP switch settings
When KP signal is input to KP IN1, set the switch S1-#3 on the PCN Board 66P3924
to ON. KP signal is positive logic: Set the switch S1-#1 on the PCN Board to OFF. KP
signal is negative logic: Set the switch S1-#1 on the PCN Board to ON
When KP signal is input to KP IN2, set the switch S1-#4 on the PCN Board 66P3924.
KP signal is positive logic: Set the switch S1-#2 on the PCN Board to OFF. KP signal
is negative logic: Set the switch S1-#2 on the PCN Board to ON
5 to 15 V
5 to 15V
Approx.
300
2K
Approx.
300
Additional Additional
Circuit Circuit
5 to 15V
Approx.
300
2K
Approx.
300
Additional Additional
Circuit Circuit
CI-6810
12 V
4. ADJUSTMENTS
less than 1 V
CI-6810
TB4
H
C
Interference Interference
Rejector Rejector
CI-6810
TB4
H
C
Interference Interference
Rejector Rejector
TB4
H
C
Interference Rejector Interference Rejector
4-11