Appendix A Gpio & Watchdog Timer; Supported Gpio Registers; Gpio Registers; A.1.1 Gpio Registers - Advantech PPC-L156T User Manual

Appendix A GPIO & Watchdog Timer
The PPC-L156T is equipped with a watchdog timer that resets the CPU
or generates an interrupt if processing comes to a standstill for any rea-
son. This feature ensures system reliability in industrial standalone or
unmanned environments.
A.1 Supported GPIO Registers
Bellow are detailed description of the GPIO addresses and programming
sample.

A.1.1 GPIO Registers

CRF0 (GP10-GP17 I/O selection register. Default 0xFF)
When set to a '1', respective GPIO port is programmed as an input port.
When set to a '0', respective GPIO port is programmed as an output port.
CRF1 (GP10-GP17 data register. Default 0x00)
If a port is programmed to be an output port, then its respective bit can be
read/written.
If a port is programmed to be an input port, then its respective bit can
only be read.
CRF2 (GP10-GP17 inversion register. Default 0x00)
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data
register.
Extended Function Index Registers (EFIRs)
The EFIRs are write-only registers with port address 2Eh or 4Eh on PC/
AT systems.
Extended Function Data Registers (EFDRs)
The EFDRs are read/write registers with port address 2Fh or 4Fh on PC/
AT systems.
PPC-L156T User Manual 32