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36
Register address 4 - STATUS3_REG
Bit
7
Table 11: Status register 4 (Register address REGADDR = 5D = 05H)
Register address 5 - STATUS4_REG
Bit
0
1
2
3
4
5
6
7
Register address 06H and 07H (Mode register 0 and 1)
Mode registers 0 and 1 control the basic functions of the camera. To ensure proper
operation, these registers are updated first during power-up. The functions of each
individual bit are shown in Tables 12, 13 and 14.
Table 12: Mode register 0 (Register address REGADDR = 6D = 06H)
Register address 6 - MODE0_REG
Bit
0
1
2
3
4
5
6
7
Table 13: Camera resolution and special functions
Enable3
0
0
1
1
03-32-00525-03
PRELIMINARY
Description
Not used = 0
Description
Error in the asynchronous communications transfer
CANCEL was active, i.e. read from non defined register
Not used = 0
Not used = 0
Not used = 0
Not used = 0
Not used = 0
Not used = 0
Name
Description
ENABLE0
Camera on, = 1 Ł Camera in operation
ENABLE1
Invert Pixel Clock, = 1 Ł phase shift of 180
degrees
ENABLE2
These bits are responsible for resolution, access
to the LUT's and the LFSR interface test
ENABLE3
EN_TOGGLE
= 1 Ł Automatic voltage switching active
EN_LL2_LOG
= 1 Ł LinLog2-response curve active
LOG
= 1 Ł Log response curve on
= 0 Ł Log response curve off
LINLOG
= 1 Ł LinLog-response curve on
= 0 Ł LinLog-response curve off
Enable2
Function
0
8 bit
1
8 bit
LUT 10-to-8
0
10 bit
1
10 bit LFSR
Comment
Digital gain x 1
Two user programmable LUT's
LUT0 factory preset digital gain x 2
LUT1 factory preset digital gain x 4
Digital gain x 1
Interface test with Linear Feedback Shift
Register (LFSR)
1M28 and 1M75 User's Manual
Default
1
0
0
0
1
0
0
0
DALSA
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