Clocks; Lclk; Figure 4 Clock Structure - Alpha Data ADM-XRC-5T2-ADV User Manual

4.5.

Clocks

The ADM-XRC-5T2-ADV is provided with numerous clock sources, as shown in Figure 4
below:
Bridge Config
(Coolrunner)
25.0 MHz
XTAL
Femto-clock
26.5625 MHz
ICS843034-01
XTAL
PCIe_RefClk (100 MHz)
Pn4 Connector

4.5.1. LCLK

The Local Bus can be used at up to 80 MHz and all timing is synchronised to LCLK between
the Bridge and User FPGAs. LCLK is generated from a 200MHz reference by a DCM within
the bridge FPGA. The minimum LCLK frequency (determined by the DCM specification) is
32MHz.
The LCLK frequency is set by writing to the board control logic. (See SDK for details and
example application).
Note: If the user FPGA application includes a DCM driven by LCLK (or one of the other
programmable clocks), the clock frequency should be set prior to FPGA configuration.
ADM-XRC-5T2-ADV User Manual
Version 1.0
Page 7
XTAL_CLK
Ctl
USERMGT_CLKB
USERMGT_CLKA
KEY
Global Clock Inputs
Clock Capable I/O
MGT Clock Inputs

Figure 4 Clock Structure

ADM-XRC-5T2-ADV User Manual
PCI
Bus
PCI-X
CLK
PCI
CLK
Bridge FPGA
(V4LX25)
REFCLK_200M
LCLK Local Bus
FCN_MGTREF
User FPGA
Virtex5
LX220T /
LX330T
PCI
RefClk
Zero-delay
Buffer
(PLL)
200 MHz
Osc.
156.25 MHz
Osc.