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PCIE_TX0_P
PCIE_TX0_N
PCIE_RX0_P
PCIE_RX0_N
PCIE_TX1_P
PCIE_TX1_N
PCIE_RX1_P
PCIE_RX1_N
PCIE_TX2_P
PCIE_TX2_N
PCIE_RX2_P
PCIE_RX2_N
PCIE_TX3_P
PCIE_TX3_N
PCIE_RX3_P
PCIE_RX3_N
PCIE_TX4_P
PCIE_TX4_N
PCIE_RX4_P
PCIE_RX4_N
PCIE_TX5_P
PCIE_TX5_N
PCIE_RX5_P
PCIE_RX5_N
PCIE_TX6_P
PCIE_TX6_N
PCIE_RX6_P
PCIE_RX6_N
PCIE_TX7_P
PCIE_TX7_N
PCIE_RX7_P
PCIE_RX7_N
4.10.
ADV212 Interface
The ADV212 is a single-chip JPEG 2000 codec from Analog Devices. It is targeted for video and
high bandwidth image compression applications that can benefit from the enhanced quality and
features provided by the JPEG 2000 (J2K)—ISO/IEC15444-1 image compression standard. The
ADM-XRC-5T2-ADV features 4 ADV212 devices which can all operate independently or in 2 banks
of 2 for full frame capabilities.
4.10.1. Signal Description
See the ADV212 data sheet and associated literature for a full description of the operation of
these pins.
Signals common to each ADV212 bank
addr<1> to <3>
mclk
vclk
hdat<0> to <31>
field
hsync
vsync
jpeg_reset_l
scomm5
ADM-XRC-5T2-ADV User Manual
Version 1.0
Page 14
Signal
FPGA Pin
AB2
AC2
AC1
AD1
AG2
AF2
AF1
AE1
AH2
AJ2
AJ1
AK1
AN2
AM2
AM1
AL1
AP2
AR2
AR1
AT1
AW2
AV2
AV1
AU1
BA1
BA2
BB2
BB3
BA6
BA5
BB5
BB4
Table 11 XMC P15 Connections
-ADV212 address bus
-ADV212 system clock
-ADV212 video data bus clock
-ADV212 host data bus
-ADV212 field sync for video mode
-ADV212 horizontal sync for video mode
-ADV212 vertical sync for video mode
-asynchronous processor reset for ADV212's
-synchronisation signal for multi-chip operation
ADM-XRC-5T2-ADV User Manual
GTP
P15 Pin
Number
114A
A1
"
B1
"
A11
"
B11
114B
D1
"
E1
"
D11
"
E11
118A
A3
"
B3
"
A13
"
B13
118B
D3
"
E3
"
D13
"
E13
122A
A5
"
B5
"
A15
"
B15
122B
D5
"
E5
"
D15
"
E15
126A
A7
"
B7
"
A17
"
B17
126B
D7
"
E7
"
D17
"
E17
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