I/O Bank Voltages; Memory Interfaces; Table 4 User Fpga I/O Bank Voltages; Table 5 Ddr Memory Bank Configuration - Alpha Data ADM-XRC-5T2-ADV User Manual

4.6.2. I/O Bank Voltages

Bank
0
1, 4, 5, 6
2
3
19, 21, 23, 25
27, 29, 31, 33
18
11, 13, 15, 17, 26
12, 20, 24

4.6.3. Memory Interfaces

The ADM-XRC-5T2-ADV has four independent banks of DDRII SDRAM when fitted with a
LX330T, SX240T or FX200T target FPGA. (Two banks with all smaller FPGAs) Each bank
consists of two memory devices in parallel to provide a 32 bit datapath. 1Gb Micron
MT47H64M16 devices are fitted as standard to provide 256MB per bank. The board will
support higher capacity devices when they become available.
The ADM-XRC-5T2-ADV has been designed for compatibility with Xilinx memory interface
cores.
Details of the signalling standards are given in the table below:
Name
DDR_ad[15:0],
DDR_ba[2:0],
DDR_rasn,
DDR_casn,
DDR_wen,
DDR_csn,
DDR_cke,
DDR_odt
DDR_ck0,
DDR_ckn0
DDR_dq[15:0]
DDR_dm[1:0]
DDR_dqs[1:0],
DDR_dqsn[1:0]
DDR_ck1,
DDR_ckn1
DDR_dq[31:16]
DDR_dm[3:2]
DDR_dqs[3:2],
DDR_dqsn[3:2]
ADM-XRC-5T2-ADV User Manual
Version 1.0
Page 10
Voltage
3.3V
1.5V
3.3V
3.3V
1.8V
1.8V
2.5V or 3.3V
3.3V
1.8V

Table 4 User FPGA I/O Bank Voltages

Direction
Output
Output
BiDir
Output
BiDir
Output
BiDir
Output
BiDir

Table 5 DDR Memory Bank Configuration

ADM-XRC-5T2-ADV User Manual
Description
Configuration I/F
DDRII SRAM
SelectMAP I/F, Serial Flash
Clocks
DDRII DRAM
DDRII DRAM (LX330T only)
Pn4 Interface
ADV212 Interface
Local Bus
I/O Standard
SSTL18_I_DCI
DIFF_SSTL18_II
SSTL18_II
SSTL18_II_DCI
DIFF_SSTL18_II
DIFF_SSTL18_II
SSTL18_II
SSTL18_II_DCI
DIFF_SSTL18_II