Board Description; Figure 1 Adm-Xrc-5T2-Adv Block Diagram - Alpha Data ADM-XRC-5T2-ADV User Manual

4.

Board Description

The ADM-XRC-5T2-ADV follows the architecture of the ADM-XRC series and decouples the
"target" FPGA from the PCI interface, allowing user applications to be designed with minimum
effort and without the complexity of PCI design.
A separate Bridge / Control FPGA interfaces to the PCI bus and provides a simple Local Bus
interface to the target FPGA. It also performs all of the board control functions including the
configuration of the target FPGA, programmable clock setup and the monitoring of on-board
voltage and temperature.
DDR2 SDRAM, SSRAM and serial flash memory connect to the target FPGA and are
supported by Xilinx or third party IP.
IO functionality is provided using multi-gigabit I/O connectors and Pn4 signals.
Bridge
Config
PCI-X /
PCI64/66
Pn1
Bridge / Control FPGA
Pn2
Pn3
32 User Defined I/O (16 LVDS pairs)
Pn14
I/O
PCIe / Serial RapidIO (x8)
Pn15
XMC
JTAG
ADM-XRC-5T2-ADV User Manual
Version 1.0
Page 3
Config Flash
Programmable
Memory
(32MB)
Local Bus (64 bit)
(Virtex4 LX25)
System
Power
Monitor
Conversion
(LM87)

Figure 1 ADM-XRC-5T2-ADV Block Diagram

ADM-XRC-5T2-ADV User Manual
Clocks
User FPGA
Virtex5
LX220T/LX330T
Serial Flash
(FFG1738)
(4MB)
DDR-II DDR-II
SDRAM SDRAM
(256MB) (256MB)
Secondary
2 x
ADV212
Primary
2 x
ADV212
Front MGT
Dual
(x8)
Lane
Link
DDR-II
SSRAM
(4MB)
DDR-II
SSRAM
(4MB)
DDR-II DDR-II
SDRAM SDRAM
(256MB) (256MB)