Pll Circuits - Icom IC-M401E Service Manual

4-2-4 POWER AMPLIFIER CIRCUIT (MAIN-E UNIT)
The power amplifier circuit amplifies the driver signal to an
output power level.
IC3 is a power module which has amplification output capa-
bilities of about 35 W with 50 mW input. The output from IC3
(pin 4) is passed through the antenna switching circuit (D14)
and is then applied to the antenna connector via the low-
pass filter.
4-2-5 APC CIRCUIT (MAIN-E UNIT)
The APC circuit stabilizes transmit output power.
The RF output signal from the power amplifier (IC3; pin 4) is
detected at the power detector circuit (D12, D13, L19, C121,
C124) and is then applied to one of the differential amplifier
inputs (Q16, pin 5) via the High/Low control circuit (Q17,
R114). The applied voltage controls the differential amplifier
output (Q16, pin 2) and the bias voltage control (Q13). Thus
the APC circuit maintains a constant output power.
• APC CIRCUIT
RF signal
Q12
from PLL
YGR
amp.
"TMUT" signal from the CPU
(LOGIC-E board; IC1, pin 83)
Q15
• PLL CIRCUIT
Loop
filter
21.25 MHz signal to the
FM IF IC (IC2, pin 2)
X1
21.25 MHz
1
Power module
IC3
2 3
Q13
Q16
APC control circuit
VCO
Q4, Q5, D3, D4
8
Phase Programmable
detector counter
Programmable
17
divider
16

4-3 PLL CIRCUITS

4-3-1 GENERAL
The PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL circuit com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by a
crystal oscillator and the divided ratio of the programmable
divider.
IC1 on the MAIN-E unit is a dual PLL IC which controls both
VCO circuits for Tx and Rx, and contains a prescaler, pro-
grammable counter, programmable divider, phase detector,
charge pump, etc.
The PLL circuit, using a one chip PLL IC (MAIN-E unit; IC1),
directly generates the transmit frequency and receive 1st IF
frequency with VCOs. The PLL sets the divided ratio based
on serial data from the CPU on the LOGIC-E board and
compares the phases of VCO signals with the reference
oscillator frequency. The PLL IC detects the out-of-step
phase and output from pins 8 for Tx and Rx. The reference
frequency (21.25 MHz) is oscillated at X1 (MAIN-E unit).
4
RF detector
D12
circuit
Vcc T5
C121
R113
R114
R112
R115
R116
Buffer
D7
Q7
Buffer
D8
Q6
Buffer
Q3
IC1 (PLL IC)
2
Prescaler
3
PSTB
4
Shift register
PCK
5
PDATA
4 - 3
L19
to antenna
D13
C124
C137
R125
"TXDET" signal to the CPU
(LOGIC-E board; IC1, pin 92)
HI/LO
Q17
to transmitter circuit
to 1st mixer circuit