Cpus And Dimms; Physical Layout; Memory Population Rules - Cisco UCS C460 M2 User Manual

CPUs and DIMMs

Physical Layout

Each CPU controls four serial memory interface (SMI) channels (see
memory riser for every two channels. There are therefore two memory risers per CPU. Each CPU channel
drives a memory buffer on a riser card, and each memory buffer converts a CPU SMI into two DDR3
subchannels that each read and write two DIMM pairs on a memory riser.
The physical layout of a memory riser is shown in
Figure 9 Memory Riser Physical Layout
1
2A
1A
2B
1B
1 Memory buffer #1
In Figure 9, the buffers and channels are:
Buffer 1, subchannel 1: slots 1B and 1D
■
Buffer 1, subchannel 2: slots 1A and 1C
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Buffer 2, subchannel 1: slots 2B and 2D
■
Buffer 2, subchannel 2: slots 2A and 2C
■

Memory Population Rules

When considering the memory configuration of your server, you should observe the following:
The minimum configuration for the server is at least one matched DIMM pair installed in a
■
memory riser on either CPU1 or CPU2 All four CPUs can run from a single DIMM pair.
DIMMs are required to be populated in pairs. DIMMs for this server are configured as
■
two-DIMM kits.
Cisco UCS C460 M2 High-Performance Rack-Mount Server
Figure 5 on page
Figure 9.
2
2 Memory buffer #2
SUPPLEMENTAL MATERIAL
14). There is one
1D
2D
1C
2C
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