Cpus And Dimms; Physical Layout; Memory Population Rules - Cisco UCS C260 M2 User Manual

SUPPLEMENTAL MATERIAL

CPUs and DIMMs

Physical Layout

Each CPU controls eight DDR3 channels. There is one memory riser for each channel. The channels are
paired (two risers per pair) and organized as follows:
CPU1: channels [A0:A1], [B0:B1], [C0:C1], [D0:D1]
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CPU2: channels [A0:A1], [B0:B1], [C0:C1], [D0:D1]
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The physical layout of the CPUs, memory risers, and memory riser channels is shown in
Figure 7 Physical Layout
CPU1 B0
CPU1 A0
CPU1 C1
CPU1 D1
CPU2 C1
CPU2 D1

Memory Population Rules

When considering the memory configuration of your server, you should observe the following:
The server must have either all two-DIMM risers or all four-DIMM risers. Do not mix riser
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types.
Memory risers must be installed in pairs on paired DDR3 channels. Paired channels are:
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—
—
Matched pairs of risers on paired DDR3 channels must have identical DIMM configurations.
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For example, the DIMM configurations must be identical on risers in A0:A1; however, the
A0:A1 configurations do not have to be identical with the B0:B1 configurations.
The minimum riser configuration is one matched pair of risers on either CPU1 or CPU2.
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Either CPU can boot and run from a single matched pair of risers.
Any riser installed on a socket that is controlled by an absent CPU is not recognized.
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CPU1
CPU2
CPU1— [A0:A1], [B0:B1], [C0:C1], [D0:D1]
CPU2— [A0:A1], [B0:B1], [C0:C1], [D0:D1]
CPU1 B1
CPU1 A1
CPU1 C0
CPU1 D0
CPU2 B0
CPU2 A0
CPU2 B1
CPU2 A1
CPU2 C0
CPU2 D0
Cisco UCS C260 M2 High-Performance Rack-Mount Server
Figure 7.