EUROCOM P180HM Service Manual page 63

Notebook computer
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Sandy Bridge 7/7 RSVD
Sandy Bridge Processor 7/7 ( RESERVED )
CFG Straps for Processor
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2
definition matches socket pin map definition
0:Lane Reversed
CFG2
R118
*1K_04
Display Port Presence Strap
1:(Default) Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0:Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG4
R113
*1K_04
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
CFG[6:5]
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG5
R112
1K_04
10 = 2 x 8 PCI Express
CFG6
R119
*1K_04
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB de assertion
CFG7
0: PEG Wait for BIOS for training
CFG7
R133
*1K_04
1.5V
R69
*0_04
R62
Q11
1K_1%_04
*AO3402L
S
D
H_CPU_RSVD6
Z0814
R85
R61
*1K_04
1K_1%_04
DRAMRST_CNTRL 3,16
1.5V
R71
*0_04
R64
Q12
1K_1%_04
*AO3402L
H_CPU_RSVD7
S
D
Z0815
R86
R63
*1K_04
1K_1%_04
DRAMRST_CNTRL 3,16
H_SNB_IVB#_PWRCTRL
On CRB
20mils
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
R60
0_04
MVREF_DQ_DIMMA 9
R70
*0_04
MVREF_CA_DIMMA 9
3.3V
R458
100K_04
H_SNB_IVB#_PWRCTRL
20mils
R72
*0_04
MVREF_CA_DIMMB 11
R73
0_04
MVREF_DQ_DIMMB 11,12
C668
0.1u_10V_X5R_04
D03A 6/16
C729
0.1u_10V_X5R_04
for Hynix DRAM
U38E
RSVD28
RSVD29
AK28
CFG[0]
RSVD30
AK29
CFG[1]
RSVD31
CFG2
AL26
CFG[2]
RSVD32
AL27
CFG[3]
AK26
CFG4
AL29
CFG[4]
CFG5
CFG[5]
RSVD33
CFG6
AL30
CFG[6]
RSVD34
CFG7
AM31
CFG[7]
RSVD35
Z0801
AM32
CFG[8]
Z0802
AM30
CFG[9]
Z0803
AM28
CFG[10]
AM26
Z0804
CFG[11]
AN28
Z0805
AN31
CFG[12]
Z0806
CFG[13]
RSVD37
Z0807
AN26
CFG[14]
RSVD38
Z0808
AM27
CFG[15]
RSVD39
Z0809
AK31
CFG[16]
RSVD40
Z0810
AN29
CFG[17]
AJ31
RSVD41
RSVD1
RSVD42
AH31
RSVD2
RSVD43
AJ33
RSVD3
RSVD44
AH33
RSVD4
RSVD45
AJ26
RSVD5
RSVD46
H_CPU_RSVD6
B4
RSVD6
RSVD47
H_CPU_RSVD7
D1
RSVD7
RSVD48
RSVD49
RSVD50
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
RSVD51
G25
RSVD12
RSVD52
G24
E23
RSVD13
D23
RSVD14
RSVD15
C30
RSVD16
RSVD53
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
RSVD54
B31
RSVD21
RSVD55
A30
C29
RSVD22
RSVD23
J20
RSVD24
B18
RSVD25
RSVD56
Z0811
A19
R459
0_04
RSVD26
RSVD57
RSVD58
J15
RSVD27
KEY
PZ98827-364B-01F
Schematic Diagrams
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
Sheet 8 of 56
AT34
AT33
AP35
Sandy Bridge 7/7
AR34
RSVD
B34
A33
A34
B35
C35
AJ32
AK32
AH27
AN35
Z0812
AM35
Z0813
AT2
AT1
AR1
B1
Sandy Bridge 7/7 RSVD B - 9

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