Intel SL3VS - Celeron 633 MHz Processor Specification page 41

C18. Snoop Cycle Generates Spurious Machine Check Exception
The processor may incorrectly generate a Machine Check Exception (MCE) when it processes a
Problem:
snoop access that does not hit the L1 data cache. Due to an internal logic error, this type of snoop cycle may
still check data parity on undriven data lines. The processor generates a spurious machine check exception as
a result of this unnecessary parity check.
A spurious machine check exception may result in an unexpected system halt if Machine
Implication:
Check Exception reporting is enabled in the operating system.
It is possible for BIOS code to contain a workaround for this erratum. This workaround would
Workaround:
fix the erratum, however, the reporting of the data parity error will continue.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C19. MOVD/MOVQ Instruction Writes to Memory Prematurely
When an instruction encounters a fault, the faulting instruction should not modify any CPU or
Problem:
system state. However, when the MMX™ technology store instructions MOVD and MOVQ encounter any of
the following events, it is possible for the store to be committed to memory even though it should be canceled:
1. If CR0.EM = 1 (Emulation bit), then the store could happen prior to the triggered invalid opcode
exception.
2. If the floating-point Top-of-Stack (FP TOS) is not zero, then the store could happen prior to executing the
processor assist routine that sets the FP TOS to zero.
3. If there is an unmasked floating-point exception pending, then the store could happen prior to the
triggered unmasked floating-point exception.
4. If CR0.TS = 1 (Task Switched bit), then the store could happen prior to the triggered Device Not
Available (DNA) exception.
If the MOVD/MOVQ instruction is restarted after handling any of the above events, then the store will be
performed again, overwriting with the expected data. The instruction will not be restarted after event 1. The
instruction will definitely be restarted after events 2 and 4. The instruction may or may not be restarted after
event 3, depending on the specific exception handler.
This erratum causes unpredictable behavior in an application if MOVD/MOVQ instructions are
Implication:
used to manipulate semaphores for multiprocessor synchronization, or if these MMX instructions are used to
write to uncacheable memory or memory mapped I/O that has side effects, e.g., graphics devices. This
erratum is completely transparent to all applications that do not have these characteristics. When each of the
above conditions are analyzed:
1. Setting the CR0.EM bit forces all floating-point/MMX instructions to be handled by software emulation.
The MOVD/MOVQ instruction, which is an MMX instruction, would be considered an invalid instruction.
Operating systems typically terminates the application after getting the expected invalid opcode fault.
2. The FP TOS not equal to 0 case only occurs when the MOVD/MOVQ store is the first MMX instruction in
an MMX technology routine and the previous floating-point routine did not clean up the floating-point
states properly when it exited. Floating-point routines commonly leave TOS to 0 prior to exiting. For a
store to be executed as the first MMX instruction in an MMX technology routine following a floating-point
routine, the software would be implementing instruction level intermixing of floating-point and MMX
instructions. Intel does not recommend this practice.
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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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