Intel SL3VS - Celeron 633 MHz Processor Specification page 26

®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
NO.
650h 651h 660h
A0 A1 A0
C82
C83 X X X
C84 X X X
C85 X X X
C86 X X X
C87 X X X
C88 X X X
C89 X X X
C90 X X X
C91 X X X
C92 X X X
18
Summary of Errata
CPUID/Stepping
665h 683h 686h 68Ah
B0 B0 C0 D0
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
Plans
6B1h 6B4h
A1 B1
SLP# is Asserted Low
X X
NoFix Incorrect assertion of
THERMTRIP# Signal
X X NoFix Under some complex
conditions, the Instructions in
the shadow of a JMP FAR
may be unintentionally
executed and retired
X X NoFix Processor Does not Flag #GP
on Non-zero Write to Certain
MSRs
IFU/BSU Deadlock May
X X NoFix
Cause System Hang
REP MOVS Operation in Fast
X X NoFix
string Mode Continues in that
Mode When Crossing into a
Page with a Different Memory
Type
POPF and POPFD
X X NoFix
Instructions that Set the Trap
Flag Bit May Cause
Unpredictable Processor
Behavior
The FXSAVE, STOS, or
X X NoFix
MOVS Instruction May Cause
a Store Ordering Violation
When Data Crosses a Page
with a UC Memory Type
Code Segment Limit Violation
X X NoFix
May Occur on 4 Gigabyte
Limit Check
FST Instruction with Numeric
X X NoFix
and Null Segment Exceptions
May Cause General Protection
Faults to be Missed and FP
Linear Address (FLA)
Mismatch
Code Segment (CS) is
X X NoFix
Incorrect on SMM Handler
when SMBASE is not Aligned
Page with PAT (Page Attribute
X X NoFix
Table) Set to USWC
(Uncacheable Speculative
Write Combine) While
Associated MTRR (Memory
Type Range Register) is UC
ERRATA