Intel SL3VS - Celeron 633 MHz Processor Specification page 106

®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
Instruction Set Reference
Section
FSTCW/FNSTCW-Store
Control Word
FSTENV/FNSTENV-Store
FPU Environment
FSTSW/FNSTSW-Store
Status Word
C3. MTRR Initialization Clarification
The following sentence should be added to the end of the first paragraph of Section 9.12.5 of the Intel
Architecture Software Developer's Manual , Volume 3: System Programming Guide: "The MTRRs must be
disabled prior to initialization or modification."
C4. Non-AGTL+ Output Low Current Clarification
In Table 6 of the Intel
®
Celeron
Symbol Parameter
V Input Low Voltage
IL
V Input High Voltage
IH
V Output Low Voltage
OL
V Output High Voltage
OH
I Output Low Current
OL
I Leakage Current for Inputs,
L
Outputs, and I/O
Notes:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. Parameter measured at 14 mA (for use with TTL inputs).
3. (0 ≤ VIN ≤ 2.5 V +5%).
4. (0 ≤ VOUT ≤ 2.5 V +5%).
5.
Specified as the minimum amount of current that the output buffer must be able to sink. However, VOL_MAX
cannot be guaranteed if this specification is exceeded.
98
Opcode Instruction
9B D9 /7 FSTCW
m2byte
9B D9 /6 FSTENV
m14/28byte
9B DD /7 FSTSW
m2byte
9B DF E0 FSTSW AX
Processor Datasheet , the note in bold should be added:
®
Min Max
-0.3 0.7
1.7 2.625
0.4
N/A 2.625
14
± 100
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Unit Notes
V
V 2.5 V +5% maximum
V 2
V All outputs are open-
drain to 2.5 V +5%
mA
5
μ A 3, 4