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* Fix will be only on Celeron processors with CPUID=068xh.
650h
651h
660h
NO.
A0
A1
A0
C1
X
X
X
C2
X
X
X
C3
X
X
X
C4
X
X
X
C5
X
X
X
C6
X
X
X
C7
X
X
X
C8
X
X
X
C9
X
X
X
C10
X
X
X
C11
X
X
X
C12
X
X
X
C13
X
X
X
C14
X
X
X
C15
X
X
X
C16
X
X
X
C17
X
X
X
C18
X
X
X
C19
X
X
X
C20
X
X
X
C21
X
X
X
®
INTEL
CELERON® PROCESSOR SPECIFICATION UPDATE
Summary of Documentation Changes
CPUID/Stepping
665h
683h
686h
68Ah
B0
B0
C0
D0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
6B1h
6B4h
Plans
A1
B1
X
X
Doc
SSE and SSE2 Instructions
Opcodes
X
X
Doc
Executing the SSE2 Variant
on a Non-SSE2 Capable
Processor
Direction Flag (DF) Mistakenly
X
X
Doc
Denoted as a System Flag
X
X
Doc
Fopcode Compatibility Mode
FCOS, FPTAN, FSIN, and
X
X
Doc
FSINCOS Trigonometric
Domain not correct
X
X
Doc
Incorrect Description of stack
X
X
Doc
EFLAGS Register Correction
X
X
Doc
PSE-36 Paging Mechanism
X
X
Doc
0x33 Opcode
X
X
Doc
Incorrect Information for SLDT
LGDT/LIDT Instruction
X
X
Doc
Information Correction
Errors In Instruction Set
X
X
Doc
Reference
X
X
Doc
RSM Instruction Set Summary
Correct MOVAPS and
X
X
Doc
MOVAPD Operand Section
DAA—Decimal Adjust AL after
X
X
Doc
Addition
DAS—Decimal Adjust AL after
X
X
Doc
Subtraction
Omission of Dependency
X
X
Doc
between BTM and LBR
I/O Permissions Bitmap Base
X
X
Doc
Addy > 0xDFFF Does not
Cause #GP(0) Fault
Wrong Field Width for MINSS
X
X
Doc
and MAXSS
Figure 15-12 PEBS Record
X
X
Doc
Format
X
X
Doc
I/O Permission Bit Map
DOCUMENTATION
CHANGES
21
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