Clock, Timers, And Reset Logic - AMD Geode SC2200 Data Book

32580B
2.5

Clock, Timers, and Reset Logic

In addition to the four main modules (i.e., GX1, Core Logic,
Video Processor and SIO) that make up the SC2200, the
following blocks of logic have also been integrated into the
SC2200:
• Clock Generators as described in Section 4.5 "Clock
Generators and PLLs" on page 87.
• Configuration Registers as described in Section 4.2
"Multiplexing, Interrupt Selection, and Base Address
Registers" on page 76.
• A WATCHDOG timer as described in Section 4.3
"WATCHDOG" on page 83.
• A High-Resolution timer as described in Section 4.4
"High-Resolution Timer" on page 85.
2.5.1 Reset Logic
This section provides a description of the reset flow of the
SC2200.
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2.5.1.1 Power-On Reset
Power-on reset is triggered by assertion of the POR# sig-
nal. Upon power-on reset, the following things happen:
• Strap balls are sampled.
• PLL4, PLL5, and PLL6 are reset, disabling their output.
When the POR# signal is negated, the clocks lock and
then each PLL outputs its clock. PLL6 is the last clock
generator to output a clock. See Section 4.5 "Clock
Generators and PLLs" on page 87.
• Certain WATCHDOG and High-Resolution Timer
register bits are cleared.
2.5.1.2 System Reset
System reset causes signal PCIRST# to be issued, thus
triggering a reset of all PCI and LPC agents. A system
reset is triggered by any of the following events:
• Power-on, as indicated by POR# signal assertion.
• A WATCHDOG reset event (see Section 4.3.2
"WATCHDOG Registers" on page 84).
• Software initiated system reset.
AMD Geode™ SC2200 Processor Data Book
Architecture Overview