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3.3.3 Advanced Chipset Control
Main
Advanced
Advanced Chipset Control
Intel VT for Directed I/O (VT-d)
Crystal Beach Configure Enable:
Force PCI-E Gen2 slot to Gen1
mode
SERR signal condition:
4GB PCI Hole Granularity:
Memory Branch Mode:
Branch 0 Rank Interleave:
Branch 0 Rank Sparing:
Branch 1 Rank Interleave:
Branch 1 Rank Sparing:
Enhanced x8 Detection:
Force ITK Config Clocking:
Reserved Branch FOR ITK
High Precision Event Timer:
Snoop filter:
↑↓
F1
Help
← →
Esc
Exit
Force PCI-E Gen2 slot to Gen1 mode
Force PCI-E Gen2 slot operate at Gen1 mode. Some PCI-E Gen1 Cards may
work abnormally on PCI-E Gen2 slot. You may use this option to select the right
mode you need when you encounter such problem.
Auto / PCI-E Gen2 / PCI-E Gen1
SERR signal condition
Select ECC error conditions that SERR# be asserted.
None / Single bit / Multiple bit/ Both
4GB PCI Hole Granularity
This feature is used to select the granularity of PCI hole for PCI resource. If
MTRRs are not enough, we may use this option to reduce the MTRR
occupation.
256MB / 512MB / 1.0GB / 2.0GB
PhoenixBIOS Setup Utility
Security
[Disabled]
[Auto]
[Single bit]
[1.0 GB]
[Interleave]
[4:1]
[Disabled]
[4:1]
[Disabled]
[Enabled]
[Disabled]
[Branch 1]
[Yes]
[Disabled]
Select Item
-/+
Select Menu
Enter
http://www.tyan.com
TPM State
Power
Change Values
Select
Sub-Menu
46
Boot
Item Specific Help
F9
Setup Defaults
F10
Save and Exit
Exit
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