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3.3.1 Advanced Chipset Control
This section allows you to fine tune the chipset configuration.
Main
Advanced Chipset Control
ICH USB Control Sub-Menu
LAN Control Sub-Menu
Crystal Beach Configure Enable
SERR signal condition
4GB PCI Hole Granularity
Memory Branch Mode
Branch 0 Rank Sparing
Enhanced x8 Detection
Force ITK Config Clocking
WatchDog Timer
Enable Multimedia Timer
Parallel ATA:
Serial ATA:
Native Mode Operation:
SATA Controller Mode Option
F1
Help
¡ ô ¡ õ
Esc
Exit
¡ ö
¡ ÷
Crystal Beach Configure Enable
Enable the configuration of memory mapped accesses to the Crystal Beach
Configuration space located in Device 8, Fn 0 and Fn 1.
Enabled / Disabled
SERR signal condition
Select ECC error conditions that SERR# be asserted.
None / Single bit / Multiple bit/ Both
4GB PCI Hole Granularity
This feature is used to select the granularity of PCI hole for PCI resource. If
MTRRs are not enough, we may use this option to reduce the MTRR
occupation.
256MB / 512MB / 1.0GB / 2.0GB
PhoenixBIOS Setup Utility
Advanced
Security
Select Item
-/+
Select Menu
Enter
Power
[Disabled]
[Single bit]
[256 MB ]
[Interleave]
[Disabled]
[Enabled]
[Disabled]
[Disabled]
[No]
[Channel 0]
[Enabled]
[Auto]
[Compatible]
Change Values
Select
Sub-Menu
43
Boot
Exit
Item Specific Help
F9
Setup Defaults
F10
Previous Values
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