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PIIX4 SERR#
Set this option to Enabled to enable the SERR# signal for the Intel
PIIX4 chip. The settings are Enabled or Disabled. The Optimal and
Fail-safe default settings are Disabled.
USB Passive Release
Set this option to Enabled to enable passive release for USB. The
settings are Enabled or Disabled. The Optimal and Fail-safe default
settings are Enabled.
PIIX4 Passive Release
Set this option to Enabled to enable passive release for the Intel PIIX4e
chip. This option must be Enabled to provide PCI 2.1 compliance. The
settings are Enabled or Disabled. The Optimal and Fail-safe default
settings are Enabled.
PIIX4 DELAYED TRANSACTION
Set this option to Enabled to enable delayed transactions for the Intel
PIIX4 chip. This option must be Enabled to provide PCI 2.1 compli-
ance. The settings are Enabled or Disabled. The Optimal and Fail-safe
default settings are Enabled.
TypeF DMA Buffer Control1 and 2
These options specify the DMA channel where TypeF buffer control is
implemented. The settings are Disabled, Channel-0, Channel-1, Chan-
nel-2, Channel-3, Channel-5, Channel-6, or Channel-7. The Optimal
and Fail-safe default settings are Disabled.
DMA-n Type
These options specify the bus that the specified DMA channel can be
used on. The settings are Normal ISA, PC/PCI, or Distributed. The
Optimal and Fail-safe default settings are Normal ISA.
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