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Chapter 4
BIOS Configuration
PCI1 to PCI0 Access
Set this option to Enabled to enable access between two different PCI
buses (PCI1 and PCI0). The settings are Enabled or Disabled. The
Optimal and Fail-safe default settings are Disabled.
Method of Memory Detection
This option determines how your system will detect the type of system
memory you have installed. Options are Auto+SPD or Auto only.
Optimal and Fail-safe default settings are Auto only.
DRAM Integrity Mode
This option sets the type of system memory checking. The settings are:
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The Optimal and Fail-safe default settings are Auto.
DRAM Refresh Rate
This option specifies the interval between refresh signals to DRAM
system memory. The settings are 15.6 us (microseconds), 31.2 us, 62.4
us, 124.8 us, or 249.6 us. The Optimal and Fail-safe default settings are
15.6 us.
Memory Hole
This option specifies the location of an area of memory that cannot be
addressed on the ISA bus. The settings are Disabled, 512KB-640KB,
or 15MB-16MB. The Optimal and Fail-safe default settings are Dis-
abled.
SDRAM RAS# to CAS# Delay
This option specifies the length of the a inserted between the RAS and
CAS signals of the DRAM system memory access cycle if SDRAM is
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