TYAN S1832DL Tiger 100 Manual page 53

High performance mainboard
Hide thumbs Also See for S1832DL Tiger 100:
Table of Contents

Advertisement

Chapter 4
BIOS Configuration
AGP Mlti-Trans Timer (AGP Clks)
This option sets the AGP multi-trans timer. The settings are in units of
AGP Clocks. The settings are Disabled, 32, 64, 96, 128, 160, 192, or
224. The Optimal default setting is 16. The Fail-safe default setting is
Disabled.
AGP Low-Priority Timer (Clks)
This option sets the AGP low priority timer. The settings are in units of
AGP Clocks. The settings are Disabled, 32, 64, 96, 128, 160, 192, or
224. The Optimal default setting is 32. The Fail-safe default setting is
Disabled.
AGP SERR#
Set this option to Enabled to enable the AGP SERR# signal. The
settings are Enabled or Disabled. The Optimal and Fail-safe default
settings are Disabled.
AGP Parity Error Response
Set this option to Enabled to enable AGP parity error response. The
settings are Enabled or Disabled. The Optimal and Fail-safe default
settings are Disabled.
8bit I/O Recovery Time
This option specifies the length of a delay inserted between consecutive
8-bit I/O operations. The settings are Disabled and from 1 to 8 Sysclk
(system clocks) in increments of one. The Optimal and Fail-safe
default settings are Disabled.
16bit I/O Recovery Time
This option specifies the length of a delay inserted between consecutive
16-bit I/O operations. The settings are Disabled and from 1 to 4 Sysclk
(system clocks) in increments of one. The Optimal and Fail-safe
default settings are Disabled.
54
http://www.tyan.com

Advertisement

Table of Contents
loading

Table of Contents