Panasonic KX-F1200 Service Manual And Technical Manual page 98

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(3) The watch dog tim_l, built-in the gate aJJay (IC404), is initialized by the CPU (IC401) about every 1.5 ms.
When the watchdo.___g__Eor occurs, pin 114 of the gate array (10404) becomes low level.
The terminal of WDERR signal is connected to the reset line, so WDERR signal works as the reset signal.
Circuit Diagram
GATE ARRAY
IC404
@l---I
+5V Ic40g 22 _ 6 !
RAMCS
CPU
I0401
MODEM
10405
IC417
21 10417 _9_
IC4O3 }
RAM
LOG BOARD
PORT IC I
p_ON BOARD
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