Panasonic KX-F1200 Service Manual And Technical Manual page 96

KX-F1200
I
Explanation Pin Distribution (IC417)
Pin No. NO. I I/O Pu/Pd
XSOFTRST
THCLK
THLAT
THDAT
NEWTHCLK
NEWTHDAT
MODE0
MODE1
MODE2
LATI0
LATI 1
LATI2
LATI3
LATI4
LATI5
LATI6
LATI7
ALE
LATO0
LATOI
LATO2
LATO3
LATO4
LATO5
LATO6
LATO7
]'N_0 --
INVII
INVI2
INVI3
INVO0
INVOI
INVO2
INVO3
XRAS
XREFSH
ADR
XRAS0
XRASI
MODE3
XRESET
RESET
VDD
VSS
i
3 I
44 I
43 I
42 I
35 O
34 O
5 I
2 I
1 I
16 I Pu
15 I Pu
14 I Pu
13 I Pu
11 I Pu
10 I Pu
9 I Pu
8 I Pu
7 I Pu
28 O
27 O
26 O
25 O
29 O
30 O
31 O
32 O
24 I
20 I
22 I
21 I
37 O
38 O
36 O
19 I/O
23 I
6 I
33 I
4O O
41 O
12 I
4 I
18 I/O
39
17
Initializing reduced circuit
Clock input
Latch input
Data input
Reduced clock output
Reduced data output
Reduction rate
Explanation
setting MODE0=0, M OVE1=1 --*100%MODE0=0, M OVE1 =0 --" 92%
MODE0=1, M OVEI=0--, 86% MODE0=I,MOVE1=1 --, 72%
Mode setting
Latch input 0
Latch input 1
Latch input 2
Latch input 3
Latch input 4
Latch input 5
Latch input 6
Latch input 7
Latch gate input
Latch output 0
Latch output 1
Latch output 2
Latch output 3
Latch output 4
Latch output 5
Latch output 6
Latch output 7
Inverter input 0
Inverter input 1
Inverter input 2
Inverter input 3
Inverter output 0
Inverter output 1
Inverter output 2
Inverter output 3
Not used
Not used
Not used
Not used
Not used
Mode setting (Fixed 5V)
Hard reset
Inverter output of XRESET._(.Not used)
Power
GND
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