Panasonic KX-F1200 Service Manual And Technical Manual page 86

KX-F1200 I
2-2, CPI.I (10401)
The KX-F1200 uses a I MP96C031 CPU operatillg at 16MHz. Read and write cycle timing chart is shown below.
P34 I---]-F
RA--'S I--TI-
P40 I-_
P41 I-'--IT
P42
CATr--rF
vcc I---FF
VREF _
INT0
INT1 I---IT
INT2 I'---T[-
INT3 I-'--IT
960 I----[]-
o_o_ o.Q.Q, o_o_ o_ o< F'F'
HHHHHRHHH HHHHHHH H
J 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 \
52 32
53 31
54 30
55 29
56 28
57 27
58 QFP64 26
59 25
60 24
61 23
62 22
63 21
64 _
20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 /
X
HHHHPIPIHHHNHHHI1 IFIHHH
-f]----I AD10
-IT---I AD9
'n--q ADS/_
"1"[--'1 AM8
q'l--'-I X2
q'[---I Xl
vss
ql----I ALE
TI--IAD7
"IT--] AD6
r[--I AD5
AD4
AD3
Pin Chip Carrier Pin Assignmets
1) Pin Bescriptions
ADO - AD15 Address/Date
A16 - A23
RD
WR
HWR
ALE
RESET
RAS
CAS
DMUX
INT1
Bus (input/output).
Address Bus (output).
Read (output, active Low). RD indicate that the CPU wants to read date from ADO - AD15.
Write (output, active Low). WR indicate that the CPU Address/Data bus (ADO - AD7) holds valid data.
Write (output, active Low). HWR indicate that the CPU Address/Data bus (AD8 - AD15) holds valid data.
Address Latch Enable (output, active High). ALE indicate that the CPU Address/Data bus (ADO - AD15) holds
valid address.
Reset (input, active Low).
Row Address Strove (output, active Low). DRAM interface.
Colomn Address Strove (output, active Low). DRAM interface.
DRAM address MUltipleX (output).
Interrupt Request (input).
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