Panasonic KX-F1200 Service Manual And Technical Manual page 95

I KX-F1200
2-_. UA I i-- AHHA¥ (lOci I)
]-his gate array has functions which reduc_n9 ,__nug_ uata fuL;u_ded on the paper, address latching and inserter after being
sent to the thermal head.
Reduction rate is possible to be set at about 72%, 86%, 92% and 100% by MODE 0 and 1.
MODE0 I MODE1
o I 1
o I o
1 I 0
1 I 1
Reduction rate
100%
92%
86%
72%
The latch latches a address of high-ranking byte AD8-15 in CPU (IC 401) to output LA8-15.
The inverter is used in the reset circuit.
IC417 Block Diagram
I ;S
from THCLK
IC404 1 /
THDAT 3 /
from CPU-MODE0-2
LATI0-7 8 /
ALE 1/
INVI0-3 4//
t
Reduced
circuit
Latch
"L
1/
1/
8//
4/
> NEWTHCLK _ to
CN407
> NEWTHDAT (Thermal head)
)LATO0-7
> INVO0-3
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