Eurotech ZEUS Technical Manual page 34

ZEUS Technical Manual
Static RAM
The PXA270 processor provides 256KB of internal memory-mapped SRAM. The
SRAM is divided into four banks, each consisting of 64KB.
The ZEUS also has an external 256KB SRAM device fitted, arranged as 256Kbit x 8-
bits. Access to the device is on 16-bit boundaries, whereby the least significant byte is
the SRAM data and the 8-bits of the most significant byte are 'don't care' bits. The
reason for this is that the PXA270 is not designed to interface to 8-bit peripherals. This
arrangement is summarized in the following data bus table:
D15 D14 D13 D12 D11 D10 D9
The external SRAM is non-volatile while the on-board coin cell battery is fitted.
Configuration EEPROM
The configuration EEPROM is interfaced directly to PXA270's I
Microchip 24AA01 1Kbit EEPROM organized as one block of 128 x 8-bit memory.
The configuration EEPROM is addressable at I²C serial bus address 0x50 and is
accessed in fast-mode operation at 400KB/s.
© 2007 Eurotech Ltd Issue D
Most significant byte
Don't Care
Detailed hardware description
Least significant byte
D8 D7 D6 D5 D4
SRAM Data
2
D3 D2 D1 D0
C controller. It is a
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