Reset Circuit; Memoryback-Up Circuit - Epson DLQ-3000 Service Manual

2.3.2 Reset Circuit

Figure 2-12 is a block diagram of the reset circuit.
voltage becomes unstable due to power on/off switching.
The circuit detects the +5V line leading edge with IC 14. The threshold voltage is set atapprox. 4.2
A reset signal is input into gate array E05A88 and CPU, then supplied to each of the devices to
reset them.
2.3.3 Memory Back-up Circuit
Figure 2-13 is a block diagram of this circuit.
When the power is turned off, mainly the following data will be backed up to EEPROM (IC16).
TOF, TEAR OFF FUNCTION, character fonts, panel configuration
USER DEFINED CHARACTER
Set values for mechanism control (for state control of all the sensors)
. Adjusted values for mechanism control (e.g. Bid Adjustment)
. Boot strap program flag (for loading program of the Flash EEPROM)
Data to be backed up is written by the CPU, i.e. by setting the NMI port to Low.
The back-up monitor circuit shown in Figure 2-14 is in the A/D converter of the CPU. The +35
signal (at P21) for the EEPROM and writes back-up data into the EEPROM.
The back-up data can be stored in this way, before the power source voltage drops completely.
Figure 2-13. Memory Back-up Circuit Block Diagram
TYPE-B l/F
o
3.3k
Vcc
GND
Figure 2-12. Reset Circuit Diagram
CPU
P60 'A Reading
P61
I
Operating Principle
CPU
8
GA
88
DO
2-19