Table of Contents
Advertisement
time, all processor data requests must first be sent to every processor in the
system so that each processor can determine if a more recent copy of the
requested data is in that processor cache.
Snooping traffic is an important factor affecting performance and scaling for all
SMP systems. The overhead of this communication becomes greater with an
increase in the number of processors in a system. Also, faster processors result
in a greater percentage of time spent performing snooping because the speed of
the communications does not improve as the processor clock speed increases,
since latency is largely determined by the speed of the front-side bus.
Its easy to see that increasing the number of processors and using faster
processors results in greater communication overhead and memory controller
bottlenecks. But unlike traditional SMP designs, which send every request from
every processor to all other processors, greatly increasing snooping traffic, the
x455 has a more optimal design. The XceL4 cache in the x455 improves
performance because it filters most snooping operations.
The IBM XceL4 cache improves scalability with more than four processors
because it also caches remote data addresses. So, before any processor request
is sent across the scalability link to a remote processor, the memory controller
and cache controller determine whether the request should be sent at all. To do
this, each cache controller keeps a directory of all the addresses of all data
stored in all remote processor caches. By checking this directory first, the cache
controller can determine if a data request must be sent to a remote processor
and only send the request to that specific SMP Expansion Module where the
processor caching the requested data is located.
The majority of data requests not found in the XceL4 cache can be sent directly
to the memory controller to perform memory look-up without any remote
processor-to-processor communication overhead. The directory-based
coherency protocol used by the XceL4 cache greatly improves scalability of the
x455 because processor-to-processor traffic is greatly reduced.
By using this cache and providing fast local memory access to all processors,
typical bottlenecks that are associated with large SMP systems using a single
memory controller design are eliminated.
IBM Eserver xSeries 455 Planning and Installation Guide
38
Advertisement
Table of Contents
