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Advantech ROM-7720 Design Manual
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Advantech ROM-7720 Design Manual

Advantech ROM-7720 Design Manual

Carrier board arm-based qseven 2.1 module with nxp i.mx8quad max arm cortex a72/53 processor
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Carrier Board
Design Guide
 
 
 
 
 
ROM-7720
 
 
 
 
 
Arm-based Qseven 2.1 Module
with NXP i.MX8Quad Max
arm
Cortex™A72/53 Processor
®

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Summary of Contents for Advantech ROM-7720

  • Page 1                               Carrier Board       Design Guide   ROM-7720           Arm-based Qseven 2.1 Module with NXP i.MX8Quad Max Cortex™A72/53 Processor ®...
  • Page 2   Chapter     Introduction  ............................... ‐ 6 ‐     About This Document  ...................... ‐ 6 ‐     Signal Table Terminology ...................... ‐ 6 ‐     Terminology  .......................... ‐ 6 ‐     Reference Documents ...................... ‐ 9 ‐     Revision History  ........................ ‐ 9 ‐     Qseven Interfaces  ............................ ‐ 10 ‐     Qseven Connector Layout ..................... ‐ 10 ‐     Connector Pin‐out ......................... ‐ 11 ‐    ...
  • Page 3       2.7.6 USB Client Considerations ..................... ‐ 39 ‐     2.7.7 USB2.0 Trace Length Guidelines  .................... ‐ 40 ‐     USB3.0 Signal Definitions ...................... ‐ 41 ‐     2.8.1 USB3.0 Trace Length Guidelines .................... ‐ 43 ‐     USB Connector EMI / ESD Protection .................. ‐ 44 ‐     SDIO Interface  ........................ ‐ 46 ‐     2.10.1 SDIO Signal Definitions ...................... ‐ 46 ‐     2.10.2 The Qseven module SDIO support UHS‐I.................. ‐ 48 ‐     2.10.3 SDIO Interface Routing Guidelines .................. ‐ 49 ‐     High Definition Audio / AC97 / I2S Audio Signals .............. ‐ 50 ‐...
  • Page 4       Miscellaneous Signals ...................... ‐ 72 ‐     2.18.1 Miscellaneous Signals ...................... ‐ 72 ‐     2.18.2 Watchdog Control Signals  ...................... ‐ 73 ‐     Thermal Signals  ........................ ‐ 74 ‐     2.19.1 Thermal Interface ........................ ‐ 74 ‐     2.19.2 Thermal Signals Routing Guidelines .................. ‐ 74 ‐     2.19.3 Thermal Signals Trace Length Guidelines ................ ‐ 74 ‐     Fan Control Implementation .................... ‐ 75 ‐     2.20.1 Fan Control Interface ...................... ‐ 75 ‐     Optional MIPI‐CSI2 Feature Interface Signals ............... ‐ 76 ‐...
  • Page 5         FIGURE 2.1 CONVENTIONS AND TERMINOLOGY ...................... ‐ 10 ‐   FIGURE 2.2 MODULE BLOCK DIAGRAM .......................... ‐ 15 ‐ FIGURE 2.3 ROM-7720 SUPPORTS 2X PCIE 3.0 WITH 1-LANE.  ................ ‐ 17 ‐     FIGURE 2.4 THE QSEVEN MODULE PCIE WAKE# ARCHITECTURE  .................. ‐ 19 ‐   FIGURE 2.5 THE QSEVEN MODULE’S PCIE REST# ARCHITECTURE  .................. ‐ 19 ‐   FIGURE 2.7 TOPOLOGY FOR PCI EXPRESS DEVICE DOWN. .................... ‐ 20 ‐   FIGURE 2.6 TOPOLOGY FOR PCI EXPRESS SLOT CARD. ...................... ‐ 20 ‐   FIGURE 2.8 LAN GROUND PLANE SEPARATION  ......................... ‐ 25 ‐   FIGURE 2.9 LAN LED CIRCUIT.  ............................ ‐ 26 ‐   FIGURE 2.10 TOPOLOGY FOR ETHERNET JACK ........................ ‐ 27 ‐  ...
  • Page 6           TABLE 1.1 CONVENTIONS AND TERMINOLOGY........................ ‐ 6 ‐   TABLE 2.1 ROM‐7720 PIN‐OUT  ............................ ‐ 11 ‐   TABLE 2.2 Q7 R2.0 AND Q7 R2.1 DIFFERENCE TABLE ...................... ‐ 14 ‐   TABLE 2.3 ROM‐7720 SUPPORTED FEATURES ........................ ‐ 14 ‐   TABLE 2.4 MODULE TERMINATIONS .......................... ‐ 15 ‐   TABLE 2.5 GENERAL PURPOSE PCI EXPRESS SIGNAL DESCRIPTIONS  ................. ‐ 17 ‐   TABLE 2.6 PCI EXPRESS* SLOT CARD / DEVICE DOWN TRACE LENGTH GUIDELINES  ............ ‐ 20 ‐   TABLE 2.7 LAN INTERFACE SIGNAL DESCRIPTIONS  ...................... ‐ 22 ‐   TABLE 2.8 ETHERNET TRACE LENGTH GUIDELINES ...................... ‐ 27 ‐   TABLE 2.9 SATA SIGNAL DEFINITIONS  .......................... ‐ 29 ‐   TABLE 2.10 SATA TRACE LENGTH GUIDELINES ........................ ‐ 31 ‐   TABLE 2.11 USB CONTROL SIGNAL DEFINITIONS ...................... ‐ 33 ‐   TABLE 2.12 USB2.0 SIGNAL DESCRIPTIONS ........................ ‐ 36 ‐  ...
  • Page 7 It includes Signal Descriptions, Routing Guidelines, and Trace Length Guidelines. The main purpose is designing t h e Carrier Board for helping customers fast and easy using the module of Advantech to be designed.   Signal Table Terminology Table 1 below describes the terminology used in this section for the Signal Description tables.
  • Page 8   Terminology Description Embedded DisplayPort (eDP) is a digital display interface standard produced by the Video Electronics Standards Association (VESA) for digital interconnect of Audio and Video. EEPROM Electrically Erasable Programmable Read-Only Memory Electrical Fast Transient Electromagnetic Interference Electrostatic Discharge ExpressCard A PCMCIA standard built on the latest USB 2.0 and PCI Express buses.
  • Page 9   Open-Drain Power Pin Printed Circuit Board PCI Express Peripheral Component Interface Express. Next-generation high speed (PCIe) serialized I/O bus PCI Express Lane One PCI Express Lane is a set of 4 signals that contains two differential lines for Transmitter and two differential lines for Receiver. Clocking information is embedded in the data stream.
  • Page 10 Qseven Specification ATX12V Power Supply Design Guide Rev. 2.01   Revision History Revision Date PCB Rev. Changes Mar 31, 2020 A101-6 ROM-7720 design for Q7 R2.1 Sep 8, 2020 A101-6 Add power consumption              ...
  • Page 11   Qseven Interfaces Qseven Connector Layout GF1A GND_1 GND_2 GBE_MDI3- GBE_MDI2- GBE_MDI3+ GBE_MDI2+ GBE_LINK100# GBE_LINK1000# GBE_MDI1- GBE_MDI0- GBE_MDI1+ GBE_MDI0+ GBE_LINK# GBE_ACT# GBE_CTREF SUS_S5# WAKE# SUS_S3# SUS_STAT#/GPO0 PWRBTN# SLP_BTN#/GPII1 LID_BTN#/GPII0 GND_3 GND_4 GF1B GND_5 PWGIN BATLOW#/GPII2 RSTBTN# CAN0_TX CAN0_RX SATA0_TX+ SATA1_TX+ DP_LANE3+/TMDS_CLK+ USB_SSTX1- SATA0_TX-...
  • Page 12     Connector Pin-out   Table 2.1 ROM-7720 Pin-out Edge Fingers Edge Fingers ROM-7720 Even number ROM-7720 number V2.1 V2.1 GBE_MDI3- GBE_MDI2- GBE_MDI3- GBE_MDI2- GBE_MDI3+ GBE_MDI2+ GBE_MDI3+ GBE_MDI2+ GBE_LAN100_LINK# GBE_LINK100# GBE_LINK1000# GBE_LAN1000_LINK# GBE_MDI1- GBE_MDI0- GBE_MDI1- GBE_MDI0- GBE_MDI1+ GBE_MDI0+ GBE_MDI1+ GBE_MDI0+...
  • Page 13   USB_P5- / USB_P4- / USB2.0/ USB2.0/ USB_SSTX2- USB_SSRX2- USB3.0 USB3.0 USB_SSTX2- USB_SSRX2- USB_P5+ / USB_P4+ / USB2.0/ USB2.0/ USB_SSTX2+ USB_SSRX2+ USB3.0 USB3.0 USB_SSTX2+ USB_SSRX2+ USB_2_3_OC# USB_0_1_OC# USB_2_3_OC# USB_0_1_OC# USB_P3- USB_P2- USB_P3- USB_P2- USB_P3+ USB_P2+ USB_P3+ USB_P2+ USB_VBUS USB_OTG_ID USB_VBUS USB_ID USB_OTG1_DN USB_P0-...
  • Page 14   DP_LANE0- / HDMI_CTRL_CL HDMI_TX0_DDC_SC DP/HDMI HDMI_TX0_DATA2_N DP / HDMI TMDS_LANE2- HDMI HDMI_TX0_HPD# DP_HPD# HDMI_HPD# DP_HPD# PCIE_CPU_REFCLK PCIE PCIE PCIE_WAKE# PCIE_CLK_REF+ PCIE_WAKE# 100M_P PCIE_CPU_REFCLK PCIE PCIE PCIE_PERST# PCIE_CLK_REF- PCIE_RST# 100M_N PCIE PCIE PCIE3_TX+ PCIE3_RX+ PCIE PCIE PCIE3_TX- PCIE3_RX- PCIE PCIE PCIE2_TX+ PCIE2_RX+ PCIE...
  • Page 15                       Table 2.3 ROM-7720 Supported Features V2.1 System I/O ROM-7720 ARM/RISC Configuration Revision Min / Max V2.1 ARM/RISC PCI Express lanes 0 (x1 link) / 4 2 (x1 link) (i.MX8)
  • Page 16   Module Block Diagram     Figure 2.2 Module Block Diagram   Module Terminations   Table 2.4 Module Terminations Signal Name Series Termination (On Parallel Termination (On Notes Module) Module) PCIE(0,1)_TX +/- 0.22uF      PCIE_WAKE#   10K pull‐up to 3.3V    PCIE_RST#  ...
  • Page 17     4.7K pull‐up to 3.3V    GP0_I2C_DAT   4.7K pull‐up to 3.3V    GP1_I2C_CLK   4.7K pull‐up to 3.3V    GP1_I2C_DAT   10K pull‐up to 1.7V    JTAG_TMS   10K pull‐up to 1.7V    JTAG_TDI 10K pull‐up to 1.7V  JTAG_TRST# 10K pull‐down to GND JTAG_TCK Pull‐up to 3.3V  BATLOW# 100K pull‐up to 1.7V  PWGIN Pull‐up 2.2k to 3.3V  PWRBTN# Pull‐up 10k to 3.3V  RSTBTN# Pull‐up to 3.3V  WAKE# Pull‐up to 3.3V  SLP_BTN#        ...
  • Page 18 They are used for simultaneous transmission in each direction. The ROM-7720 supports only 1x PCIe Gen 3 x2, not support 2x pcie.                                           ...
  • Page 19   PCIE1_RX+ PCIe channel 1. Receive Input differential pair. I PCIE PCIE1_RX Carrier Board: Device - Connect AC Coupling cap 0.22uF in PCIe device difference pair p/n and near to Device. Slot - Connect to PCIe Conner pins p/n. N/C if not used PCIE1_TX+ PCIe channel 1.
  • Page 20   3. The Qseven module combined the two signals of PCIe0_WAKE# and PCIe1_WAKE# with two diodes to be the PCIe_wake# signal. Figure 2.4 The Qseven module PCIe WAKE# Architecture 4. The Qseven module provides one PCI Express Reset signal on pin 158 of the Qseven connector(referenced as PLT_RST#) in the example schematics.
  • Page 21   2.4.2. PCI Express* Trace Length Guidelines Figure 2.7 Topology for PCI Express Slot Card. Figure 2.6 Topology for PCI Express Device Down. Table 2.6 PCI Express* Slot Card / Device Down Trace Length Guidelines Parameter Main Route Guidelines Notes Signal Group PCI Express* expansion  ...
  • Page 22   Carrier Board Length   Length matching Differential pairs (intra-pair): Max. ±5 mils   REFCLK+ and REFCLK- (intra-pair): Max. ±15mils Reference Plane GND referencing preferred   Min 40-mil trace edge-to-major plane edge spacing GND stitching vias required next to signal vias if transitioning layers between GND layers Power referencing acceptable if stitching caps are used Carrier Board Via Max.
  • Page 23   LAN Interface Qseven modules provide at least one 10/100/1000BaseT Gigabit Ethernet LAN port compliant with the IEEE 802.3ab specification 2.5.1 LAN Signal Definitions The LAN interface of the Qseven module consists of 4 pairs of low voltage differential pair signals designated from 'GBE_MDI0' (+ and -) to 'GBE_MDI3' (+ and -) plus additional control signals for link activity indicators.
  • Page 24   module's PHY and may be as low as 0V and as high as 3.3V. The reference voltage output should be current limited to the module. In a case in which the reference is shorted to ground, the current must be limited to 250mA or less.
  • Page 25   2.5.2 LAN Implementation Guidelines The most critical component in the LAN interface is the isolation magnetics connected directly to the MDI differential pair signals of the Qseven module. It should be carefully qualified for Return Loss, Insertion Loss, Open Circuit Inductance, Common Mode Rejection, and Crosstalk Isolation to pass the IEEE conformance tests and EMI tests.
  • Page 26   2.5.5 LAN Ground Plane Separation The isolated separation between the analog ground plane and the digital ground plane is recommended. If this is not implemented properly then bad ground plane partitioning could cause serious EMI emissions and degrade analog performance due to ground bounce noise. The plane area underneath the magnetic module should be left empty.
  • Page 27   2.5.6 LAN Link Activity and Speed LED The Qseven module has four 3.3V push/pull outputs to directly drive activity, speed indication, and link status LEDs. The 3.3V standby voltage should be used as an LED supply voltage so that the link activity can be viewed during the system standby state. Since LEDs are likely to be integrated into an RJ45 connector with an integrated magnetics module, the LED traces need to be routed away from potential sources of EMI noise.
  • Page 28   2.5.7 LAN Trace Length Guidelines Figure 2.10 Topology for Ethernet Jack Table 2.8 Ethernet Trace Length Guidelines Parameter Main Route Guidelines Notes Signal Group GBE0_MDIx+, GBE0_MDIx- Differential Impedance Target 100 Ω ±10% Single End 50Ω ±10% Spacing between Min. 50mils  ...
  • Page 29   2.5.8 Reference Ground Isolation and Coupling The Carrier Board should maintain a well-designed analog ground plane around the components on the primary side of the transformer between the transformer and the RJ-45 receptacle. The analog ground plane is bonded to the shield of the external cable through the RJ-45 connector housing.
  • Page 30   SATA The ROM‐7720 would not support this function in the present, and it just revered these pins for the  future.     Table 2.9 SATA Signal Definitions Signal Pin# Description Note SATA0_RX+ I SATA   SATA0_RX- SATA0_TX+ O SATA SATA0_TX- SATA1_RX+ I SATA SATA1_RX- SATA1_TX+ O SATA SATA1_TX- SATA_ACT# O 3.3V Able CMOS to drive 10mA  ...
  • Page 31   Notes: No support SATA. 2.6.1 SATA Routing Guidelines NA      2.6.2 General SATA Routing Guidelines ‐ 30 ‐   ...
  • Page 32   2.6.3 SATA Trace Length Guidelines     Figure 2.11 Topology for SATA   Table 2.10 SATA Trace Length Guidelines Parameter Main Route Guidelines Notes Signal Group SATA   Differential Impedance Target   Single End   Signal length available for the  ...
  • Page 33   USB2.0 Ports The Universal Serial Bus interface of the Qseven module is compliant to USB 1.1 as well as USB 2.0 and USB 3.0 specification. Qseven specifies a minimum configuration of 3 USB 2.0 host ports for ARM architectures respectively 4 USB 2.0 ports for Intel architectures up to a maximum of 8 ports on both platforms.
  • Page 34   Simple resettable PolySwitch devices are capable of fulfilling the requirements of USB overcurrent protection and therefore can be used as a replacement for power distribution switches. Fault status signals are connected by a pullup resistor to VCC_3V3_SBY on COM Express Module.
  • Page 35   USB_ID 92 USB ID pin. CMOS 3.3V Configures the mode of the USB Port 1. The resistance of this pin measured to the ground is used to determine whether USB Port 1 is going to be used as a USB Client to enable/ disable USB Client support.
  • Page 36     Figure 2.12 Carrier Board USB-OTG Reference schematic module support 3 x ports USB2.0 (USB_P0 /USB_P2 /USB_P3) Qseven These signals can be implemented into USB Type-A connectors or other USB2.0 devices. Or can be connected with USB3.0 signals into USB3.0 connectors. Consider the ESD and EMI it should be added common chock and ESD protect IC in the circuit design.
  • Page 37       Figure 2.13 Carrier Board USB2.0 and 3.0 Reference schematic   Table 2.12 USB2.0 Signal Descriptions Signal Pin# Description Note USB_P0+ USB Port 0, data + or D+   USB_P0- USB Port 0, data - or D- USB2.0 Carrier board: Device - Connect to D+/- Conn.
  • Page 38   These pins used as a USB client port and this port also USB_P1+   can be OTG function. USB_P1- USB-OTG Carrier board: Device - Connect to D+/- Conn. - Connect 90Ω @100MHz Common Choke in series and ESD suppressors to GND. N/C if not used USB_P2+ 90 USB Port 2, data + or D+...
  • Page 39   Avoid stubs on high-speed USB signals because stubs cause signal reflections and  affect signal quality. If a stub is unavoidable in the design, the total of all the stubs on a particular line should not be greater than 200 mils (5.08 mm). ...
  • Page 40   2.7.6 USB Client Considerations Precautions at the carrier board level must be taken to protect against voltage spikes and ESD to ensure robust operation of the host detection circuitry after multiple connect/disconnect events. A clamping diode may be used to minimize ESD, and a bulk capacitor should be placed on +5V USB client rail to avoid excessive voltage spikes.
  • Page 41   2.7.7 USB2.0 Trace Length Guidelines     Figure 2.16 Topology for USB2.0         Table 2.13 USB2.0 Trace Length Guidelines Parameter Main Route Guidelines Notes Signal Group USB_P0/P1/P2/P3   Differential Impedance Target 90 Ω ±10%   Single End 50Ω...
  • Page 42   USB3.0 Signal Definitions USB3.0 Super Speed is supported on USB2 and USB3 and defines data rates up to 5Gbps. Therefore these ports have two additional differential signal pairs SSRX and SSTX module support 3x USB3.0, 3xUSB2.0, and 1x USB-OTG Qseven Table 2.14 USB3.0 Signal Descriptions Signal...
  • Page 43   USB Superspeed transmit signal differential pair. O USB3.0 USB_SSTX0+ The module has integrated AC Coupling USB_SSTX0- Carrier Board: Control the differential impedance (Zdiff) of the SS_TX+/- signals to 85 Ω, +/-5 Ω. Device - Connect to StdA_SSRX+/- Conn. - Connect 90Ω @100MHz USB3.0 Common Mode Choke in series and USB3.0 ESD suppressors to GND, the value of Chock depends on EMI and signal integrity performance.
  • Page 44   2.8.1 USB3.0 Trace Length Guidelines Figure 2.177 Topology for USB3.0 Table 2.15 USB3.0 Trace Length Guidelines Parameter Main Route Guidelines Notes Signal Group USB3.0   Differential Impedance Target 85 Ω ±10%   Single End 50Ω ±10%   Spacing between pairs-to-pairs Min.
  • Page 45   USB Connector EMI / ESD Protection USB2.0: Testing has shown that common mode chokes can provide the required noise attenuation. The design should include a common mode choke footprint to provide a stuffing option in the event the choke is needed to pass EMI testing. The below figure shows the schematic of a typical common mode choke and ESD suppression components.
  • Page 46   Further common mode choke information can be found on the high-speed USB Platform Design Guides available at www.usb.org. To improve the EMI behavior of the USB interface, the design should include common mode chokes, which have to be placed as close as possible to the USB connector signal pins. Common mode chokes can provide required noise attenuation but they also distort the signal quality of full-speed and high-speed signaling.
  • Page 47   SDIO Interface SDIO (Secure Digital I/O) provides an easy to implement the solution for high-speed data I/O combined with low power consumption. SDIO cards are fully compatible with SD memory cards. This includes mechanical, electrical, power, signaling, and software compatibility. SDIO hosts can drive SD cards and MMC (MultiMediaCards) as well as SDIO cards that provide functions such as Ethernet or WLAN, GPS receivers, Bluetooth, modems, etc.
  • Page 48   SDIO_CMD SDIO Command/Response. This signal is used for I/O 3.3V   card initialization and command transfers. During CMOS initialization mode, this signal is open drain. During command transfer, this signal is in push-pull mode. Carrier Board: Connect to CMD of SDIO/MMC device or card. It can add 22 ohms in series that close to the connector or device to reduce the inrush voltage and EMI issue.
  • Page 49   2.10.2 The Qseven module SDIO support UHS-I. Figure 2.19 SDIO SLOT Reference Circuit ‐ 48 ‐   ...
  • Page 50   2.10.3 SDIO Interface Routing Guidelines       Figure 2.20 Topology for SDIO     Table 2.17 SDIO Trace Length Guidelines Parameter Main Route Guidelines Notes Signal Group SDIO   Single End 50Ω ±10%   CMD/Data/DATA to CLK Maximum +/- 10mils  ...
  • Page 51   High Definition Audio / AC97 / I2S Audio Signals Since Version 2.0Qseven modules support either High Definition Audio (HDA), AC'97, or I²S for implementing audio functionality. module only supports I2S. Qseven   2.11.1 Audio Codec Signal Descriptions     Table 2.18 Audio Codec Signal Descriptions Signal Pin#...
  • Page 52   I2S_SDI I 3.3V HD Audio Serial Data Input from Codec.   CMOS Multiplexed with I2S Serial Data Input from Codec. Carrier Board: Connected to CODEC Date Output   Note: 1. I/O Orientation: Input denotes a signal flow to the module and output denotes a signal flow from the module.
  • Page 53   Route digital power and signal traces over the digital ground plane.  Position the bypassing and decoupling capacitors close to the IC pins with wide traces  to reduce impedance. Place the crystal or oscillator (depending on the codec used) as close as possible to ...
  • Page 54   2.11.3 Audio Trace Length Guidelines   Figure 2.21 Topology for Audio       Table 2.19 Audio Trace Length Guidelines Parameter Main Route Guidelines Notes Signal Group Audio   Single End 50Ω ±15%   Nominal Trace Space within Min. 15mils  ...
  • Page 55   LVDS The Qseven 2.1 specification defines the LVDS flat panel interface that optionally supports up to two 24-bit LVDS channels. It permits dual pixel, two-channel data transmission between the host and flat panel display. Each LVDS channel consists of up to five LVDS signal pairs transmitting a serial bit stream directly to the LVDS flat panel or an external LVDS receiver.
  • Page 56     Signal Pin# Description Note LVDS_A_CK+ LVDS channel A differential clock pair O LVDS   LVDS_A_CK- Carrier Board: Connect 100Ω @100MHz Common Choke in series to Receiver – Connect 100Ω termination between +/- node. Conn. – Follow the Pin definition. N/C if not use LVDS_B0+ LVDS channel B differential signal pair 0...
  • Page 57       Signal Pin# Description Note LVDS_PPEN LVDS flat panel power enable.   3.3V, Carrier Board: CMOS Connect to enable control of LVDS panel power circuit. N/C if not used LVDS_BKLEN LVDS flat panel backlight enable high active signal  ...
  • Page 58     Signal Pin# Description Note LVDS_BLC_CLK LVDS_BLC_CLK: I/O 3.3V, In Qseven definition, this pin is OD. We used this signal to be the second DisplayID DDC signal to CMOS implement two LVDS panels if the LVDS panel has the same I2C ID. It was pull-up to 4.7K ohm on Module.
  • Page 59   2.12.2 LVDS Trace Length Guidelines     Figure 2.22 Topology for LVDS   Table 2.21 LVDS Trace Length Guidelines Parameter Main Route Guidelines Notes Signal Group LVDS   Differential Impedance Target 100Ω ±10%   Single End 50Ω ±10%   Signal length to the LVDS connector 4”...
  • Page 60   HDMI Table 2.22 HDMI Signal Definitions Signal Shared With Pin# Description Notes TMDS differential pair clock lines. TMDS_CLK- 1  Carrier Board: TMDS_CLK+ TMDS Connected ESD protection IC and Add common chock 100ohm for EMI. N/C if not used. TMDS differential pair lines lane 0. TMDS_LANE0- 1 ...
  • Page 61   separate channels of uncompressed digital audio and auxiliary control data during the horizontal and vertical blanking intervals of the TMDS video stream. The Qseven® specification defines a single-link HDMI interface with a pixel clock rate of up to 165 MHz. The appropriate TMDS receive and transmit differential signal pair, as well as additional control signals, can be found on the Qseven®...
  • Page 62   Level Shifters and pull-up to 5V for HDMI_CTRL_CLK and HDMI_CTRL_DAT shall be on the carrier board +V3.3 +V5_HDMI C1201 100nF R1207 10K 1%_1/16W 10%_16V C1202 100nF U1201 10%_16V VCC_A VCC_B HDMI_X_CTRL_DAT R1201 R1204 HDMI_CTRL_DAT HDMI_X_CTRL_CK R1202 R1205 HDMI_CTRL_CK NXP_NTS0104GU12 Figure 2.24 HDMI DDC 3.3V to 5V Level Shift  ...
  • Page 63   2.13.2 HDMI Routing Guidelines     Figure 2.26 Topology for HDMI       Table 2.23 HDMI Trace Length Guidelines Parameter Main Route Guidelines Notes Signal Group HDMI (TMDS)   Differential Impedance Target 100 Ω ±10%   Single End 50Ω...
  • Page 64   Reference Plane GND referencing preferred.   Min 40-mil trace edge-to-major plane edge spacing. Carrier Board Via Usage Max. 2 vias.   AC coupling capacitors (if required)   Notes: 2.13.3 ESD Protection HDMI signals are subjected to ESD strikes due to plugging in of the devices through the HDMI cable and frequent human contact that can destroy both the HDMI host and devices on the platform.
  • Page 65   The HDMI 2.0 Specification requires that 8 kV of ESD strikes be tolerated. The ESD protection devices should be placed as close to the HDMI connector as possible so that when ESD strikes occur, the discharges can be quickly absorbed or diverted to the ground/power plane before it is coupled to another signal path nearby.
  • Page 66   CAN Interface Controller Area Network (CAN or CAN-bus) is a message based protocol designed specifically for automotive applications but now is also used in other areas such as industrial automation and medical equipment. Starting with Qseven Specification revision 1.20, Qseven modules can optionally support one CAN bus.
  • Page 67   2.14.2 Interface Routing Guidelines It should be routed as a differential pair signal with 120 Ohm differential impedance. The end points of CAN bus should be terminated with 120 Ohms or with 60 Ohms from the CAN_H line and 60 Ohms from the CAN_L line to the CAN Bus reference voltage. Check your CAN transceiver application notes for further details on termination.
  • Page 68   SPI – Serial Peripheral Interface Bus The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a potentially lower-cost alternative for system devices such as EEPROM and flash components. Starting with Qseven Specification revision 1.20, Qseven modules can optionally support one SPI interface.
  • Page 69   SPI_CLK Clock from Module to Carrier SPI O CMOS –   Connect to SPI 3.3V Suspend Flash - Series Clock pin 6 Device - Series Clock N/C if not used 2.15.2 SPI Routing Guidelines     2.15.3 SPI Trace Length Guidelines  ...
  • Page 70   General Purpose I2C Bus Interface The I2C (Inter-Integrated Circuit) bus is a two-wire serial bus originally defined by Philips. The bus is used for low-speed (up to 400kbps) communication between system ICs. The Qseven specification defines several I2C interfaces that are brought to the Module connector for use on the Carrier.
  • Page 71 The maximum amount of capacitance allowed on the Carrier General Purpose I2C bus lines (I2C_DAT, I2C_CK) is specified by Advantech’s Module. The Carrier designer is responsible for ensuring that the maximum amount of capacitance is not exceeded and the rise/fall times of the signals meet the I2C bus specification.
  • Page 72   UART 2.17.1 UART interface Signal Definitions   Table 2.31 Serial Interface Signal Definitions Signal Pin# Description Note UART0_TX Serial Data Transmitter O 3.3V CMOS   Max 1mA UART0_RX Serial Data Receiver I 3.3V CMOS   ≥ 5 mA UART0_CTS# Handshake signal, ready to send data I 3.3V CMOS  ...
  • Page 73   Miscellaneous Signals 2.18.1 Miscellaneous Signals     Table 2.33 Miscellaneous Signal Definitions Signal Pin# Description Note WDTRIG# Watchdog trigger signal. This signal restarts I 3.3V   the watchdog timer of the Qseven module on CMOS the falling edge of a low active pulse. ≥...
  • Page 74   2.18.2 Watchdog Control Signals   If the Watchdog timer has expired without a software or hardware trigger occurrence, the Qseven module will signal this with a high-level output on the 'WDOUT' (Watchdog event indicator) signal. In the Qseven module, there is one HW watchdog function to monitor the system will kernel panic or not.
  • Page 75   Thermal Signals 2.19.1 Thermal Interface Qseven modules provide the 'THRM#' and 'THRMTRIP#' signals, which are used for system thermal management. In most current system platforms, thermal management is closely associated with system power management. For more detailed information about the thermal management capabilities of the Qseven module refer to the module's user's guide.
  • Page 76   Fan Control Implementation 2.20.1 Fan Control Interface module supported FAN_PWMOUT to control the fan speed, and we don’t read Qseven the fan speed.     Table 2.35 Fan Control Signal Definitions Signal Description Note FAN_PWMOUT The primary functionality is fan speed control. Uses the O 3.3V 1 ...
  • Page 77   Optional MIPI-CSI2 Feature Interface Signals module supports 4 data lanes of camera0 and 2 data lanes fo camera1 on the Qseven module. Please check the MIPI-CSI signal definition and Pinout. The CSI connector part number on the Module is IMSA-9671S-39Y912 and the manufacture is IRISO Electronics Co.,Ltd..
  • Page 78         Figure 2.34 Recommend size of FPC (Copy from IMSA-9671S-39Y912 of IRISO Table 2.36 On-Board Camera Signal Definitions Signal Description I/O Type 3.3V +/- 5% supply voltage to power the camera 3.3V Power CAM_PWR device Output 3.3V +/- 5% supply voltage to power the camera 3.3V Power CAM_PWR device...
  • Page 79   CAM0_I2C_CLK Camera 0 Control Interface, CLK. (I²C like interface) CMOS 1.8V OD O CAM0_I2C_DAT Camera 0 Control Interface, DATA. (I²C like interface) CMOS 1.8V OD I/O CAM0_ENA# Camera 0 Enable (low active) CMOS 1.8V Master Clock may be used by Cameras to drive it's MCLK CMOS 1.8V internal PLL with a Frequency range: 6...27 MHz...
  • Page 80   Power General Power requirements Qseven modules are designed to be driven with a single +5V input power rail. Additionally, two optional power rails are specified by Qseven to provide a +5V standby voltage (5V- Always) on the Qseven module as well as a +3V Real-Time Clock (RTC) supply voltage, which is provided by a battery cell located on the carrier board.
  • Page 81   Power Management Signals Table 3.1 Power Management Signal Definitions Signal Pin# Description Note PWGIN High active input for the Qseven module indicates that the I 1.8V 1  carrier board all power from the power supply is ready. Pull-up on the module. The carrier board only triggers a ≥...
  • Page 82   RSTBTN# Reset button input. This is an input pin and driven low by I 3.3V 1  the external circuit to reset the Qseven module. Pull-up on module. The carrier board only triggers a low Qseven ≥ 10 mA to GND for active. Carrier Board: Connect to Reset button N/C if...
  • Page 83   SUS_S3# The Qseven module sends this signal high to turn on all O 3.3V   of the power rails on the carrier board. The Qseven CMOS module doesn’t support the S3 or S5 domain, Please max. used the SUS_STAT# be the carrier board sleep event. 1 mA High for turn on the carrier board power rails, Low for shut down.
  • Page 84   Power Up Control The power-up control is responsible for switching the Qseven V2.0/V2.1 reference carrier board on or off when a power-up or a power-down event occurs. A power event can be generated by pressing the power button or by another system event, which can originate from or be detected by the Qseven module's chipset.
  • Page 85   no leakage current happens. After power off, please remove the DC source and insert it again when there is no power button key.   Figure 3.2 The +V5_MXM(VCC) power rail design with load switch. AT Mode POWER UP SEQUENCE POWER OFF +V12A to +V5A >...
  • Page 86         1st stage 2nd stage CARRIER_PGOOD 0.5A QSEVEN 2.1 MODULE VDD_RTC Carrier Board AND GATE CR2032 +V5_MXM Load SW 2.5A CARRIER_PWR_ON Regulator +V12A +V5A JACK Load SW HDMI 9.2A 4.2A 0.5A 11.5A USBx3 CARRIER_PWR_ON 0.2A 0.5A M2_PWR_EN +M2_3V Load SW +V3A...
  • Page 87   RTC Battery The Real-Time Clock (RTC) is responsible for maintaining the time and date even when the Qseven module is not connected to the main power supply. Usually, a +3V lithium battery cell is used to supply the internal RTC of the module. The Qseven specification defines an extra power pin 'VCC_RTC', which connects the RTC of the module to the external battery.
  • Page 88   Electrical Characteristics Absolute Maximum Ratings     Table 4.1 Absolute Maximum Ratings module UNIT Qseven 4.75 (5-5%) 5.25 (5+5%) Power VCC_5V_SB 4.75 (5-5%) 5.25 (5+5%) RTC Battery     DC Characteristics     Table 4.2 Maximum Ratings NXP i.MX 8QuadMax, MICRON_MT53D512M32D2DS-053 AIT:D 4GB Power Plane Maximum Power Consumption Symbol...