DIGITAL-LOGIC MICROSPACE MSM286 Series Technical User's Manual page 14

DIGITAL-LOGIC AG
MSM286 Manual V6.4
IRQ2 is used as soon a PCCARD card is pluged in !
/Master, input B32
This signal is used with a DRQ line to gain control of the system. A processor or DMA controller on
the I/0 channel may issue a DRQ to a DMA channel in cascade mode and receive a /DACK.
THIS SIGNAL IS NOT AVAILABLE ON A F8680A DESIGN !
/MEMCS16, input B2
MEMCS16 Chip Select signals the system board if the present data transfer is a 1 wait-state, 16-bit,
memory cycle. It must be derived from the decode of LA17 through LA23. /MEMCS16 should be
driven with an open collector (300 ohm pullup) or tri-state driver capable of sinking 2OmA.
THIS SIGNAL IS NOT AVAILABLE ON A F8680A DESIGN !
/MEMR input/output A12
These signals instruct the memory devices to drive data onto the data bus. /MEMR is active on all
memory read cycles. /MEMR may be driven by any microprocessor or DMA controller in the system.
When a microprocessor on the I/0 channel wishes to drive /MEMR, it must have the address lines
valid on the bus for one system clock period before driving /MEMR active. The signal is active low.
/MEMW, input/output A11
These signals instruct the memory devices to store the data present on the data bus. /MEMW is ac-
tive in all memory read cycles. /MEMW may be driven by any microprocessor or DMA controller in
the system. When a microprocessor on the I/O channel wishes to drive /MEMW, it must have the ad-
dress lines valid on the bus for one system clock period before driving /MEMW active. Both signals
are active low.
PS4 B10
PS4 signal for selection of display type. LCD = low / CRT = high.
Programmingvoltage VPP2 B15
Programming voltage for JEIDA card.
OSC, output A30
Oscillator (OSC) is a high-speed clock with a 70 nanosecond period (14.31818 MHz). This signal is
not synchronous with the system clock. It has a 50% duty cycle.
RESETDRV, output A2
Reset Drive is used to reset or initiate system logic at power-up time or during a low line-voltage out-
age. This signal is active high. When the signal is active all adapters should turn off or tri-state all
drivers connected to the I/O channel. This signal is driven by the permanent Master.
/REFRESH, input/output A19
This signal is used to indicate a refresh cycle and can be driven by a microprocessor on the I/0 chan-
nel. This signal is active low.
SAO-SA19, LA17 - LA23 input/output
Address bits 0 through 19 are used to address memory and I/0 devices within the system. These 20
address lines, allow access of up to 16 MBytes of memory. SAO through SA19 are gated on the sys-
tem bus when BALE is high and are latched on the falling edge of BALE. These signals are generated
by the microprocessors or DMA controllers. They may also be driven by other microprocessor or DMA
14