DIGITAL-LOGIC MICROSPACE MSM286 Series Technical User's Manual page 13

DIGITAL-LOGIC AG
MSM286 Manual V6.4
3 T PC104 B
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AEN, output C11
Address Enable is used to degate the microprocessor and other devices from the I/O channel to allow
DMA transfers to take place. low = CPU Cycle, high = DMA Cycle
BALE, output A28
Address Latch Enable is provided by the bus controller and is used on the system board to latch valid
addresses and memory decodes from the microprocessor. BALE is forced high during DMA cycles.
DACK[O..3, 5..7], output
DMA Acknowledge 0 to 3 and 5 to 7 are used to acknowledge DMA requests (DRQO through DRQ7).
They are active low. This signal indicates that a DMA operation can begin.
DRQ[O..3, 5..7], input
DMA Requests 0 through 3 and 5 through 7 are asynchronous channel requests used by peripheral
devices and the I/O channel microprocessors to gain DMA service (or control of the system). A re-
quest is generated by bringing a DRQ line to an active level. A DRQ line must be held high until the
corresponding DMA Request Acknowledge (DACK/) line goes active. DRQO through DRQ3 will per-
form 8-bit DMA transfers; DRQ5-7 are used for 16 accesses (not in F8680).
/IOCHCK, input C1
IOCHCK/ provides the system board with parity (error) information about memory or devices on the
I/O channel. low = parity error , high = normal operation
IOCHRDY, input C10
I/O Channel Ready is pulled low (not ready) by a memory or I/O device to lengthen I/O or memory
cycles. Any slow device using this line should drive it low immediately upon detecting its valid ad-
dress and a Read or Write command. Machine cycles are extended by an integral number of one
clock cycle ( 67 nanoseconds). This signal should be held low for no more than 2.5 microseconds.
low = wait, high = normal operation
/IOCS16, input B4
I/O 16 bit Chip Select signals the system board that the present data transfer is a 16-bit, 1 wait-state,
I/0 cycle. It is derived from an address decode. /IOCS16 is active low and should be driven with an
open collector (300 ohm pullup) or tri-state driver capable of sinking 2OmA. The signal is driven
based only on SA15-SAO (not /IOR or /IOW) when AEN is not asserted.
/IOR, input/output A14
I/O Read instructs an I/O device to drive its data onto the data bus. It may be driven by the system
microprocessor or DMA controller, or by a microprocessor or DMA controller resident on the I/O
channel. This signal is active low.
/IOW, input/output A13
I/O Write instructs an I/O device to read the data on the data bus. It may be driven by any microproc-
essor or DMA controller in the system. This signal is active low.
IRQ[2-7]., input
These signals are used to tell the microprocessor that an I/O device needs attention. An interrupt re-
quest is generated when an IRQ line is raised from low to high. The line must be held high until the
microprocessor acknowledges the interrupt request .
Onboard used interrupt: IRQ3, 4 , 6 , 7
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