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SN8P2602B
USER'S MANUAL
Preliminary Specification Version 0.4
www.DataSheet4U.com
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
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8-Bit Micro-Controller
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Preliminary Version 0.4
SN8P2602B
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Summary of Contents for SONIX SN8P2602B
- Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.
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Page 2: Amendment History
Remove power consumption(Pc). Add Fcpu limitation by noise filter enable. Modify ELECTRICAL CHARACTERISTIC. VER 0.3 Jan.2007 Add Marking Definition. Modify ELECTRICAL CHARACTERISTIC. Modify RST/P1.5/VPP PIN DISCRIPTION. VER 0.4 Mar.2007 Add Instruction Table. www.DataSheet4U.com Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 2... -
Page 3: Table Of Contents
DIRECTLY ADDRESSING MODE ..................32 2.2.3 INDIRECTLY ADDRESSING MODE ..................32 STACK OPERATION........................33 2.3.1 OVERVIEW ..........................33 2.3.2 STACK REGISTERS ......................... 34 2.3.3 STACK OPERATION EXAMPLE..................... 35 RESET ..............................36 Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 3... - Page 4 P1W WAKEUP CONTROL REGISTER ................... 57 INTERRUPT............................58 OVERVIEW............................. 58 INTEN INTERRUPT ENABLE REGISTER................... 59 INTRQ INTERRUPT REQUEST REGISTER ................60 GIE GLOBAL INTERRUPT OPERATION ..................60 PUSH, POP ROUTINE ........................61 Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 4...
- Page 5 ABSOLUTE MAXIMUM RATING ....................87 10.2 ELECTRICAL CHARACTERISTIC....................87 OTP PROGRAMMING PIN......................88 11.1.1 The pin assignment of Easy Writer transition board socket: ........... 88 11.1.2 Programming Pin Mapping: ....................89 PACKAGE INFORMATION ......................90 Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 5...
- Page 6 SOP 18 PIN ..........................91 12.1.3 SSOP 20 PIN ..........................92 MARKING DEFINITION......................... 93 13.1 INTRODUCTION ..........................93 13.2 MARKING INDETIFICATION SYSTEM..................93 13.3 MARKING EXAMPLE ........................94 13.4 DATECODE SYSTEM ........................94 www.DataSheet4U.com Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 6...
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Page 7: Product Overview
Slow Wake-up CHIP Stack IHRC I/O PWM Buzzer Package (word) (Byte) Level Mode Mode Pin No. SN8P1602B DIP18/SOP18/SSOP20 SN8P2622 0.5K DIP18/SOP18/SSOP20 SN8P2602A DIP18/SOP18/SSOP20 SN8P2602B DIP18/SOP18/SSOP20 SN8P2611 DIP14/SOP14 SN8P2612 DIP18/SOP18/SSOP20 SN8P2613 DIP20/SOP20/SSOP20 Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 7... -
Page 8: System Block Diagram
1.2 SYSTEM BLOCK DIAGRAM EXTERNAL INTERNAL (Low Voltage Detector) HIGH OSC. LOW RC FLAGS WATCHDOG TIMER TIMING GENERATOR www.DataSheet4U.com PWM 0 PWM 0 BUZZER 0 BUZZER0 SYSTEM REGISTERS INTERRUPT TIMER & COUNTER CONTROL Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 8... -
Page 9: Pin Assignment
P1.0 P0.0/INT0 P1.5/RST/VPP XOUT/P1.4 P5.0 P5.7 P5.1 P5.6 P5.2 P5.5 P5.3 P5.4/BZ0/PWM0 SN8P2602BP www.DataSheet4U.com SN8P2602BS P1.2 P1.1 P1.3 P1.0 P0.0/INT0 P1.5/RST/VPP XOUT/P1.4 P5.0 P5.7 P5.1 P5.6 P5.2 P5.5 P5.3 P5.4/BZ0/PWM0 SN8P2602BX Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 9... -
Page 10: Pin Descriptions
P5 [7:0] Built-in pull-up resisters. Port 5.4 bi-direction pin. Schmitt trigger structure as input mode. P5.4/BZ0.PWM0 Built-in pull-up resisters. TC0 ÷ 2 signal output pin for buzzer and PWM output pin. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 10... -
Page 11: Pin Circuit Diagrams
Latch Open-Drain P1OC Port 1.4 structure: Pull-Up Oscillator PnM, PnUR Code Option Input Bus Output Output Bus Latch Int. Osc. Port 1.5 structure: Ext. Reset Code Option Int. Bus Int. Rst Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 11... -
Page 12: Central Processor Unit (Cpu)
Jump to user start address 0001H General purpose area 0007H 0008H Interrupt vector User interrupt vector 0009H User program 000FH 0010H 0011H General purpose area 03FCH End of user program 03FDH Reserved 03FEH 03FFH Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 12... -
Page 13: Reset Vector (0000H)
Example: Defining Reset Vector ; 0000H START ; Jump to user program address. … www.DataSheet4U.com ; 0010H, The head of user program. START: … ; User program … ENDP ; End of program Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 13... -
Page 14: Interrupt Vector (0008H)
; End of interrupt service routine RETI … START: ; The head of user program. … ; User program … START ; End of user program … ENDP ; End of program Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 14... - Page 15 ENDP ; End of program. Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
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Page 16: Look-Up Table Description
Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Example: INC_YZ macro. INC_YZ MACRO INCMS ; Z+1 ; Not overflow INCMS ; Y+1 ; Not overflow ENDM Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 16... - Page 17 ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 … TABLE1: 0035H ; To define a word (16 bits) data. 5105H 2012H … Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 17...
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Page 18: Jump Table Description
; ACC = 3, jump to A3POINT SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size. - Page 19 SN8P2602B 8-Bit Micro-Controller Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”. B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A ; The number of the jump table listing is five. A0POINT ; ACC = 0, jump to A0POINT A1POINT ;...
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Page 20: Checksum Calculation
; If Not jump to checksum calculate CHECKSUM_END ; If Yes checksum calculated is done. Y_ADD_1: INCMS ; Increase Y ; Jump to checksum calculate CHECKSUM_END: … … END_USER_CODE: ; Label of program end Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 20... -
Page 21: Code Option Table
If users define watchdog as “Always_On”, assembler will Enable “Watch_Dog” automatically. Fcpu code option is only available for High Clock. Fcpu of slow mode is Fosc/4 (the Fosc is internal low clock). Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 21... -
Page 22: Data Memory (Ram)
General purpose area “ “ “ 02Fh BANK 0 080h 80h~FFh of Bank 0 store system registers (128 bytes). “ “ System register “ www.DataSheet4U.com “ “ 0FFh End of bank 0 area Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 22... -
Page 23: System Register
TC0M = TC0 mode register. TC0C = TC0 counting register. TC0R = TC0 auto-reload data buffer. WDTR = Watchdog timer clear register. STKP = Stack pointer buffer. STK0~STK3 = Stack 0 ~ stack 3 buffer. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 23... -
Page 24: Bit Definition Of System Register
3. One-bit name had been declared in SN8ASM assembler with “F” prefix code. 4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers. 5. For detail description, please refer to the “System Register Quick Reference Table” Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 24... -
Page 25: Accumulator
“PUSH”, “POP” save and load ACC, PFLAG data into buffers. Example: Protect ACC and working registers. INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 25... -
Page 26: Program Flag
1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero. Note: Refer to instruction set table for detailed information of C, DC and Z flags. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 26... -
Page 27: Program Counter
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. A, #12H ; To skip, if ACC = 12H. CMPRS C0STEP ; Else jump to C0STEP. … … C0STEP: Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 27... - Page 28 DECS C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: DECMS instruction: BUF0 DECMS C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 28...
- Page 29 ; If ACC = 0, jump to A0POINT A1POINT ; ACC = 1, jump to A1POINT A2POINT ; ACC = 2, jump to A2POINT A3POINT ; ACC = 3, jump to A3POINT … … Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 29...
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Page 30: Y, Z Registers
; Clear @YZ to be zero DECMS ; Z – 1, if Z= 0, finish the routine CLR_YZ_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 30... -
Page 31: R Registers
Bit 2 Bit 1 Bit 0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Read/Write After reset Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application. www.DataSheet4U.com Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 31... -
Page 32: Addressing Mode
B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 32... -
Page 33: Stack Operation
Low Byte STKP = 3 STK3H STK3L www.DataSheet4U.com STKP + 1 STKP - 1 STKP = 2 STK2H STK2L STKP = 1 STK1H STK1L STKP STKP STKP = 0 STK0H STK0L Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 33... -
Page 34: Stack Registers
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0 STKnL Read/Write After reset STKn = STKnH , STKnL (n = 3 ~ 0) Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 34... -
Page 35: Stack Operation Example
(PC) to the program counter registers. The Stack-Restore operation is as the following table. STKP Register Stack Buffer Stack Level Description STKPB1 STKPB0 High Byte Low Byte STK3H STK3L STK2H STK2L STK1H STK1L STK0H STK0L Free Free Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 35... -
Page 36: Reset
High Detect Watchdog Low Detect Overflow Watchdog Normal Run Watchdog Reset Watchdog Stop System Normal Run System Status System Stop Power On External Watchdog Delay Time Reset Delay Reset Delay Time Time Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 36... -
Page 37: Power On Reset
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the watchdog timer function. Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 37... -
Page 38: Brown Out Reset
DC low battery condition. When turn off the AC power, the VDD drops slowly and through the dead-band for a while. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 38... -
Page 39: The System Operating Voltage Decsription
2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips) and use external reset (“ Zener diode reset circuit”, “Voltage bias reset circuit”, “External reset IC”). The structure can improve noise effective and get good EFT characteristic. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 39... - Page 40 Delay Time The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by www.DataSheet4U.com...
- Page 41 IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead-band. The external reset information is described in the next section. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 41...
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Page 42: External Reset
The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference. Note: The reset circuit is no any protection against unusual power or brown out reset. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 42... -
Page 43: Diode & Rc Reset Circuit
PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener specification. Select the right zener voltage to conform the application. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 43... -
Page 44: Voltage Bias Reset Circuit
When power drops below the reset detect voltage, the system reset would be triggered, and then system executes reset sequence. That makes sure the system work well under unstable power situation. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 44... -
Page 45: External Reset Ic
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can improve all power variation. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 45... -
Page 46: System Clock
Fcpu = Flosc/4. SONIX provides a “Noise Filter” controlled by code option. In high noisy situation, the noise filter can isolate noise outside and protect system works well. The minimum Fcpu of high clock is limited at Fhosc/4 when noise filter enable. -
Page 47: Oscm Register
Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal low-speed oscillator will be stopped. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 47... -
Page 48: System High Clock
High_Clk code option. The start up time of crystal/ceramic and RC type oscillator is different. RC type oscillator’s start-up time is very short, but the crystal’s is longer. The oscillator start-up time decides reset time length. 4MHz Crystal 32768Hz Crystal 4MHz Ceramic Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 48... -
Page 49: Crystal/Ceramic
“R” value is to change frequency. 50P~100P is good value for “C”. XOUT pin is general purpose I/O pin. Note: Connect the R and C as near as possible to the VDD pin of micro-controller. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 49... -
Page 50: External Clock Signal
XIN pin. XOUT pin is general purpose I/O pin. External Clock Input XOUT www.DataSheet4U.com Note: The GND of external oscillator circuit must be as near as possible to VSS pin of micro-controller. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 50... -
Page 51: System Low Clock
; oscillator called power down mode (sleep mode). Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1 (32K, watchdog disable) bits of OSCM register. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 51... -
Page 52: System Clock Measurement
; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P0.0 ; Measure the Fcpu frequency by oscilloscope. Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC frequency. www.DataSheet4U.com Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 52... -
Page 53: System Operation Mode
All active All active All inactive P0, P1, T0 Wakeup source P0, P1, Reset Reset EHOSC: External high clock ILRC: Internal low clock (16K RC oscillator at 3V, 32K at 5V) Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 53... -
Page 54: System Mode Switching
; Set CPUM1 = 1. Note: If T0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can wakeup the system backs to the previous operation mode. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 54... - Page 55 Note: During the green mode with T0 wake-up function, the wakeup pins, reset pin and T0 can wakeup the system back to the last mode. T0 wake-up period is controlled by program and T0ENB must be set. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 55...
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Page 56: Wakeup
The wakeup time is as the following. The wakeup time = 1/Fosc * 2048 = 0.512 ms (Fosc = 4MHz) The total wakeup time = 0.512 ms + oscillator start-up time Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 56... -
Page 57: P1W Wakeup Control Register
Bit 0 P15W P14W P13W P12W P11W P10W Read/Write After reset Bit[5:0] P10W~P15W: Port 1 wakeup function control bits. 0 = Disable P1n wakeup function. 1 = Enable P1n wakeup function. www.DataSheet4U.com Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 57... -
Page 58: Interrupt
INT0 Trigger Interrupt Vector Address (0008H) T0IRQ 3-Bit Enable T0 Time Out Global Interrupt Request Signal TC0IRQ TC0 Time Out Latchs Gating Note: The GIE bit must enable during all interrupt operation. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 58... -
Page 59: Inten Interrupt Enable Register
0 = Disable T0 interrupt function. 1 = Enable T0 interrupt function. Bit 5 TC0IEN: TC0 timer interrupt control bit. 0 = Disable TC0 interrupt function. 1 = Enable TC0 interrupt function. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 59... -
Page 60: Intrq Interrupt Request Register
0 = Disable global interrupt. 1 = Enable global interrupt. Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE Note: The GIE bit must enable during all interrupt operation. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 60... -
Page 61: Push, Pop Routine
. D a t a S h e e t 4 U . c o m INT_SERVICE START: … INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector … ENDP Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 61... -
Page 62: Int0 (P0.0) Interrupt Operation
; P00IRQ = 0, exit interrupt vector B0BCLR FP00IRQ ; Reset P00IRQ … ; INT0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 62... -
Page 63: T0 Interrupt Operation
A, #74H B0MOV T0C, A ; Reset T0C. … ; T0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 63... -
Page 64: Tc0 Interrupt Operation
A, #74H B0MOV TC0C, A ; Reset TC0C. … ; TC0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 64... -
Page 65: Multi-Interrupt Operation
; Jump to exit of IRQ B0BTS0 FTC0IRQ ; Check TC0IRQ INTTC0 ; Jump to TC0 interrupt service routine INT_EXIT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 65... -
Page 66: I/O Port
; Set all ports to be output mode. B0MOV P0M, A B0MOV P1M, A B0MOV P5M, A B0BCLR P1M.2 ; Set P1.2 to be input mode. B0BSET P1M.2 ; Set P1.2 to be output mode. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 66... -
Page 67: I/O Pull Up Register
Note: P1.5 is input only pin and without pull-up resister. The P1UR.5 keeps “1”. Example: I/O Pull up Register A, #0FFH ; Enable Port0, 1, 5 Pull-up register, B0MOV P0UR, A B0MOV P1UR, A B0MOV P5UR, A Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 67... -
Page 68: I/O Open-Drain Register
Example: Disable P1.0 to open-drain mode and output low. A, #0 ; Disable P1.0 open-drain function. B0MOV P1OC, A Note: After disable P1.0 open-drain function, P1.0 mode returns to last I/O mode. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 68... -
Page 69: I/O Port Data Register
Example: Write one bit data to output port. B0BSET P1.3 ; Set P1.3 and P5.5 to be “1”. B0BSET P5.5 B0BCLR P1.3 ; Set P1.3 and P5.5 to be “0”. B0BCLR P5.5 Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 69... -
Page 70: Timers
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the main routine of the program. Main: A,#5AH ; Clear the watchdog timer. B0MOV WDTR,A … CALL SUB1 CALL SUB2 … … … MAIN Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 70... - Page 71 ; I/O and RAM are correct. Clear watchdog timer and www.DataSheet4U.com ; execute program. B0BSET FWDRST ; Only one clearing watchdog timer of whole program. … CALL SUB1 CALL SUB2 … … … MAIN Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 71...
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Page 72: Timer 0 (T0)
T0RATE[2:0]: T0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. … 110 = fcpu/4. 111 = fcpu/2. Bit 7 T0ENB: T0 counter control bit. 0 = Disable T0 timer. 1 = Enable T0 timer. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 72... -
Page 73: T0C Counting Register
500 ms 1953.125 us Fcpu/8 2.048 ms 8 us 250 ms 976.563 us Fcpu/4 1.024 ms 4 us 125 ms 488.281 us Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 73... -
Page 74: T0 Timer Operation Sequence
Set T0 interrupt interval time. www.DataSheet4U.com A,#7FH B0MOV T0C,A ; Set T0C value. Set T0 timer function mode. B0BSET FT0IEN ; Enable T0 interrupt function. Enable T0 timer. B0BSET FT0ENB ; Enable T0 timer. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 74... -
Page 75: Timer/Counter 0 (Tc0)
TC0 / 2 P5.4 TC0R Reload ALOAD0, TC0OUT Data Buffer TC0 Rate (Fcpu/2~Fcpu/256) PWM0OUT Compare TC0CKS TC0ENB Fcpu Load TC0C 8-Bit Binary Up TC0 Time Out Counting Counter INT0 (Schmitter Trigger) CPUM0,1 Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 75... -
Page 76: Tc0M Mode Register
1 = Enable TC0 timer. Note: When TC0CKS=1, TC0 became an external event counter and TC0RATE is useless. No more P0.0 interrupt request will be raised. (P0.0IRQ will be always 0). Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 76... -
Page 77: Tc0C Counting Register
500 ms 1953.125 us Fcpu/8 2.048 ms 8 us 250 ms 976.563 us Fcpu/4 1.024 ms 4 us 125 ms 488.281 us Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 77... -
Page 78: Tc0R Auto-Load Register
TC0R initial value = N - (TC0 interrupt interval time * input clock) = 256 - (10ms * 4MHz / 4 / 64) = 256 - (10 * 4 * 10 / 4 / 64) = 100 = 64H Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 78... -
Page 79: Tc0 Clock Frequency Output (Buzzer)
; Enable TC0 output to P5.4 and disable P5.4 I/O function B0BSET FALOAD1 ; Enable TC0 auto-reload function B0BSET FTC0ENB ; Enable TC0 timer Note: Buzzer output is enable, and “PWM0OUT” must be “0”. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 79... -
Page 80: Tc0 Timer Operation Sequence
; 0~63. B0BSET FALOAD0 ; ALOAD0, TC0OUT = 10, PWM cycle boundary is B0BCLR FTC0OUT ; 0~31. B0BSET FALOAD0 ; ALOAD0, TC0OUT = 11, PWM cycle boundary is B0BSET FTC0OUT ; 0~15. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 80... - Page 81 Set TC0 timer function mode. B0BSET FTC0IEN ; Enable TC0 interrupt function. B0BSET FTC0OUT ; Enable TC0OUT (Buzzer) function. B0BSET FPWM0OUT ; Enable PWM function. Enable TC0 timer. B0BSET FTC0ENB ; Enable TC0 timer. www.DataSheet4U.com Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 81...
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Page 82: Pwm0 Mode
Overflow per 16 count The Output duty of PWM is with different TC0R. Duty range is from 0/256~255/256. …… …… …… …… TC0 Clock TC0R=00H High TC0R=01H High TC0R=80H High TC0R=FFH Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 82... -
Page 83: Tcxirq And Pwm Duty
(Duty Range 0~63) TC0 Overflow, TC0IRQ = 1 0xFF TC0C Value 0x00 PWM0 Output (Duty Range 0~31) TC0 Overflow, TC0IRQ = 1 0xFF TC0C Value 0x00 PWM0 Output (Duty Range 0~15) Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 83... -
Page 84: Pwm Duty With Tcxr Changing
2 and period 4, and the new duty is changed in next period. By the way, system can avoid the PWM not changing or H/L changing twice in the same cycle and will prevent the unexpected or error operation. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 84... -
Page 85: Pwm Program Example
TC0R, A INCMS BUF0 ; Get the new TC0R value from the BUF0 buffer defined by ; programming. B0MOV A, BUF0 B0MOV TC0R, A Note: The PWM can work with interrupt request. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 85... -
Page 86: Instruction Table
2. If branch condition is true then “S = 1”, otherwise “S = 0”. 3. “I” of “B0MOV M,I” doesn’t support “E6h” and “E7h”. 4. “M” of “B0XCH” doesn’t support 0x80~0xFF system registers. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 86... -
Page 87: Electrical Characteristic
Low voltage reset level. Fcpu = 1 MHz. LVD Voltage Vdet1 Low voltage indicator level. Fcpu = 1 MHz. Vdet2 Low voltage indicator level. Fcpu = 1 MHz *These parameters are for design reference, not tested. Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 87... -
Page 88: Otp Programming Pin
JP1 for MP transition board DIP13 DIP36 DIP14 DIP35 DIP15 DIP34 DIP16 DIP33 DIP17 DIP32 DIP18 DIP31 DIP19 DIP30 DIP20 DIP29 DIP21 DIP28 DIP22 DIP27 DIP23 DIP26 DIP24 DIP25 JP3 for MP transition board Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 88... -
Page 89: Programming Pin Mapping
SN8P2602B 8-Bit Micro-Controller 11.1.2 Programming Pin Mapping: Programming Information of SN8P2602B Chip Name SN8P2602BP/S SN8P2602BX EZ Writer OTP IC / JP3 Pin Assigment Connector Number Name Number Number 15,16 P5.0 P5.0 P1.0 P1.0 P5.1 P5.1 www.DataSheet4U.com ALSB/PDB P1.1 P1.1 Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD... -
Page 90: Package Information
22.352 22.860 23.368 0.300 7.620 0.245 0.250 0.255 6.223 6.350 6.477 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.335 0.355 0.375 8.509 9.017 9.525 θ° 0° 7° 15° 0° 7° 15° Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 90... -
Page 91: Sop 18 Pin
0.447 0.455 0.463 11.354 11.557 11.760 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.325 10.643 0.016 0.033 0.050 0.406 0.838 1.270 θ° 0° 4° 8° 0° 4° 8° Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 91... -
Page 92: Ssop 20 Pin
3.900 4.000 0.025 0.635 0.010 0.017 0.020 0.250 0.420 0.500 0.016 0.025 0.050 0.400 0.635 1.270 0.039 0.041 0.043 1.000 1.050 1.100 0.059 1.500 0.004 0.100 θ° 0° 8° 0° 8° Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 92... -
Page 93: Marking Definition
Marking Definition 13.1 INTRODUCTION There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit MCU for order or obtain information. This definition is only for Blank OTP MCU. 13.2 MARKING INDETIFICATION SYSTEM SN8 X PART No. -
Page 94: Marking Example
9=09 A=10 B=11 ..1=January Month 2=February ..9=September A=October B=November C=December 03= 2003 Year 04= 2004 05= 2005 06= 2006 ..Preliminary Version 0.4 SONiX TECHNOLOGY CO., LTD Page 94... - Page 95 SONIX product could create a situation where personal injury or death may occur.
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