SONIX SN8P26L00 Series User Manual
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SONIX SN8P26L00 Series User Manual

8-bit micro-controller
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SN8P26L00 Series
USER'S MANUAL
Preliminary Specification Version 0.2
SN8P26L34
SN8P26L32
SN8P26L321
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
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SN8P26L00 Series
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Preliminary Version 0.2
8-Bit Micro-Controller

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Summary of Contents for SONIX SN8P26L00 Series

  • Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.

  • Page 2: Amendment History

    SN8P26L00 Series 8-Bit Micro-Controller AMENDMENT HISTORY Version Date Description VER 0.1 Dec. 2006 First Issue. 1. Add SN8P26L321 pin assignment. VER 0.2 Mar. 2007 2. Add IR section. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 2...

  • Page 3: Table Of Contents

    2.2.2 DIRECTLY ADDRESSING MODE ....................36 2.2.3 INDIRECTLY ADDRESSING MODE ..................... 36 2.3 STACK OPERATION..........................37 2.3.1 OVERVIEW ............................. 37 2.3.2 STACK REGISTERS ........................38 2.3.3 STACK OPERATION EXAMPLE....................39 3 RESET ................................40 Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 3...
  • Page 4 5.3.3 P1W WAKEUP CONTROL REGISTER ..................60 6 INTERRUPT..............................61 6.1 OVERVIEW ............................61 6.2 INTEN INTERRUPT ENABLE REGISTER ..................62 6.3 INTRQ INTERRUPT REQUEST REGISTER..................63 6.4 GIE GLOBAL INTERRUPT OPERATION ..................63 Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 4...
  • Page 5 9.2.1 TC0M MODE REGISTER ....................... 93 9.2.2 TC0C COUNTING REGISTER ....................... 93 9.2.3 TC0R AUTO-LOAD REGISTER ..................... 94 9.2.4 TC0D IR DUTY CONTROL REGISTER ..................95 9.2.5 IR OUTPUT OPERATION SEQUENCE..................96 Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 5...
  • Page 6 15.1 SK-DIP 28 PIN ........................... 109 15.2 SOP 28 PIN ............................110 15.3 SSOP 28 PIN............................111 15.4 P-DIP 18 PIN ............................112 15.5 SOP 18 PIN ............................113 15.6 SSOP 20 PIN............................116 Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 6...

  • Page 7: Product Overview

    (byte) arator Buzzer Pin No. Osc. DIP18/ SN8P26L32 1-ch SOP18 DIP20/ SOP20/ SN8P26L321 2-ch SSOP20 SKDIP28/ SN8P26L34 2-ch SOP28/ SSOP28 *Note: SN8P26L321 doesn’t includes CM0O pin and comparator 0 output function. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 7...

  • Page 8: System Block Diagram

    FLAGS WATCHDOG TIMER CM0P TIMING GENERATOR CM0N Comparator 0 CM0O CM1P CM1N Comparator 1 CM1O IR OUT IROUT SYSTEM REGISTERS PWM 1 PWM1 INTERRUPT CONTROL TIMER & COUNTER BUZZER1 BUZZER 1 Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 8...

  • Page 9: Pin Assignment

    20 P2.6/CM1P P0.1/INT1 19 P2.5/CM1N 18 P2.3/CM0P P5.4/IROUT 17 P2.2/CM0N 16 XIN/P0.3 P5.0 15 XOUT/P0.4 P5.1 14 P1.3 P5.2 13 P1.2 P5.3/BZ1/PWM1 12 P1.1 P0.2/RST/VPP 10 11 P1.0 SN8P26L321P SN8P26L321S SN8P26L321X Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 9...

  • Page 10: Pin Descriptions

    Schmitt trigger structure and built-in pull-up resisters as input mode. CM1P: Analog comparator 1 positive input pin. P2.7: Port 2.7 bi-direction pin. P2.7/CM1O Schmitt trigger structure and built-in pull-up resisters as input mode. CM1O: Analog comparator 1 output pin. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 10...
  • Page 11 Schmitt trigger structure and built-in pull-up resisters as input mode. P5.3/BZ1/PWM1 BZ1: 1/2 TC1 counter output pin. PWM1: PWM1 output. P5.4: Port 5.4 bi-direction pin. P5.4/IROUT Schmitt trigger structure and built-in pull-up resisters as input mode. IROUT: IR output pin. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 11...

  • Page 12: Pin Circuit Diagrams

    Port 0.3, 0.4 structure: Pull-Up Oscillator PnM, PnUR Code Option Input Bus Output Output Bus Latch Int. Osc. Port 2 structure: Pull-Up CMnEN PnM, PnUR Input Bus Output Output Bus Latch Comparator Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 12...
  • Page 13 SN8P26L00 Series 8-Bit Micro-Controller Port 0.2 structure: Ext. Reset Code Option Int. Bus Int. Rst Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 13...

  • Page 14: Central Processor Unit (Cpu)

    Jump to user start address 0001H General purpose area 0007H 0008H Interrupt vector User interrupt vector 0009H User program 000FH 0010H 0011H General purpose area 1FFCH End of user program 1FFDH Reserved 1FFEH 1FFFH Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 14...

  • Page 15: Reset Vector (0000H)

    Example: Defining Reset Vector ; 0000H START ; Jump to user program address. … ; 0010H, The head of user program. START: … ; User program … ENDP ; End of program Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 15...

  • Page 16: Interrupt Vector (0008H)

    ; End of interrupt service routine RETI … START: ; The head of user program. … ; User program … START ; End of user program … ENDP ; End of program Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 16...
  • Page 17 ENDP ; End of program. Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.

  • Page 18: Look-Up Table Description

    Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Example: INC_YZ macro. INC_YZ MACRO INCMS ; Z+1 ; Not overflow INCMS ; Y+1 ; Not overflow ENDM Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 18...
  • Page 19 ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 … TABLE1: 0035H ; To define a word (16 bits) data. 5105H 2012H … Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 19...

  • Page 20: Jump Table Description

    ; ACC = 3, jump to A3POINT SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
  • Page 21 SN8P26L00 Series 8-Bit Micro-Controller Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”. B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A ; The number of the jump table listing is five. A0POINT ; ACC = 0, jump to A0POINT A1POINT ;...

  • Page 22: Checksum Calculation

    ; If Not jump to checksum calculate CHECKSUM_END ; If Yes checksum calculated is done. Y_ADD_1: INCMS ; Increase Y ; Jump to checksum calculate CHECKSUM_END: … … END_USER_CODE: ; Label of program end Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 22...

  • Page 23: Code Option Table

    If users define watchdog as “Always_On”, assembler will Enable “Watch_Dog” automatically. Fcpu code option is only available for High Clock. Fcpu of slow mode is Fosc/4 (the Fosc is internal low clock). Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 23...

  • Page 24: Data Memory (Ram)

    80h~FFh of Bank 0 store system registers (128 bytes). “ “ System register “ “ “ 0FFh End of bank 0 area 100h Bank 1 “ “ General purpose area “ BANK 1 “ “ 16Fh Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 24...

  • Page 25: System Register

    TC1C = TC1 counter register. TC1M = TC1 mode control register. WDTR = Watchdog timer clear register. TC1R = TC1 auto-reload buffer. STKP = Stack pointer buffer. STK0~STK7 = Stack 0 ~ stack 7 buffer. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 25...

  • Page 26: Bit Definition Of System Register

    S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 STK1L 0FDH S1PC12 S1PC11 S1PC10 S1PC9 S1PC8 STK1H 0FEH S0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0PC0 STK0L 0FFH S0PC12 S0PC11 S0PC10 S0PC9 S0PC8 STK0H Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 26...
  • Page 27 3. One-bit name had been declared in SN8ASM assembler with “F” prefix code. 4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers. 5. For detail description, please refer to the “System Register Quick Reference Table” Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 27...

  • Page 28: Accumulator

    “PUSH”, “POP” save and load ACC, PFLAG data into buffers. Example: Protect ACC and working registers. INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 28...

  • Page 29: Program Flag

    1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero. Note: Refer to instruction set table for detailed information of C, DC and Z flags. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 29...

  • Page 30: Program Counter

    If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. A, #12H ; To skip, if ACC = 12H. CMPRS C0STEP ; Else jump to C0STEP. … … C0STEP: Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 30...
  • Page 31 DECS C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: DECMS instruction: BUF0 DECMS C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 31...
  • Page 32 ; If ACC = 0, jump to A0POINT A1POINT ; ACC = 1, jump to A1POINT A2POINT ; ACC = 2, jump to A2POINT A3POINT ; ACC = 3, jump to A3POINT … … Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 32...

  • Page 33: H, L Registers

    DECMS ; L – 1, if L = 0, finish the routine CLR_HL_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … … Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 33...

  • Page 34: Y, Z Registers

    ; Clear @YZ to be zero DECMS ; Z – 1, if Z= 0, finish the routine CLR_YZ_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 34...

  • Page 35: R Registers

    Bit 2 Bit 1 Bit 0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Read/Write After reset Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 35...

  • Page 36: Addressing Mode

    B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 36...

  • Page 37: Stack Operation

    STKP = 5 STK5H STK5L STKP STKP STKP = 4 STK4H STK4L STKP = 3 STK3H STK3L STKP = 2 STK2H STK2L STKP = 1 STK1H STK1L STKP = 0 STK0H STK0L Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 37...

  • Page 38: Stack Registers

    Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0 STKnL Read/Write After reset STKn = STKnH , STKnL (n = 7 ~ 0) Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 38...

  • Page 39: Stack Operation Example

    STKP Register Stack Buffer Stack Level Description STKPB2 STKPB1 STKPB0 High Byte Low Byte STK7H STK7L STK6H STK6L STK5H STK5L STK4H STK4L STK3H STK3L STK2H STK2L STK1H STK1L STK0H STK0L Free Free Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 39...

  • Page 40: Reset

    High Detect Low Detect Watchdog Overflow Watchdog Normal Run Watchdog Reset Watchdog Stop System Normal Run System Status System Stop Power On External Watchdog Delay Time Reset Delay Reset Delay Time Time Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 40...

  • Page 41: Power On Reset

    Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the watchdog timer function. Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 41...

  • Page 42: Brown Out Reset

    DC low battery condition. When turn off the AC power, the VDD drops slowly and through the dead-band for a while. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 42...

  • Page 43: The System Operating Voltage Decsription

    2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips) and use external reset (“ Zener diode reset circuit”, “Voltage bias reset circuit”, “External reset IC”). The structure can improve noise effective and get good EFT characteristic. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 43...
  • Page 44 Delay Time The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by each MCU.
  • Page 45 IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead-band. The external reset information is described in the next section. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 45...

  • Page 46: External Reset

    The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference. Note: The reset circuit is no any protection against unusual power or brown out reset. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 46...

  • Page 47: Diode & Rc Reset Circuit

    PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener specification. Select the right zener voltage to conform the application. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 47...

  • Page 48: Voltage Bias Reset Circuit

    When power drops below the reset detect voltage, the system reset would be triggered, and then system executes reset sequence. That makes sure the system work well under unstable power situation. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 48...

  • Page 49: External Reset Ic

    The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can improve all power variation. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 49...

  • Page 50: System Clock

    Flosc. Fcpu = Flosc/4 HOSC: High_Clk code option. Fhosc: External high-speed clock / Internal high-speed RC clock. Flosc: Internal low-speed RC clock (about 16KHz@3V). Fosc: System clock source. Fcpu: Instruction cycle. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 50...

  • Page 51: Oscm Register

    Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal low-speed oscillator will be stopped. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 51...

  • Page 52: System High Clock

    High_Clk code option. The start up time of crystal/ceramic and RC type oscillator is different. RC type oscillator’s start-up time is very short, but the crystal’s is longer. The oscillator start-up time decides reset time length. 4MHz Crystal 32768Hz Crystal 4MHz Ceramic Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 52...

  • Page 53: Crystal/Ceramic

    “R” value is to change frequency. 50P~100P is good value for “C”. XOUT pin is general purpose I/O pin. Note: Connect the R and C as near as possible to the VDD pin of micro-controller. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 53...

  • Page 54: External Clock Signal

    XIN pin. XOUT pin is general purpose I/O pin. External Clock Input XOUT Note: The GND of external oscillator circuit must be as near as possible to VSS pin of micro-controller. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 54...

  • Page 55: System Low Clock

    ; oscillator called power down mode (sleep mode). Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1 (32K, watchdog disable) bits of OSCM register. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 55...

  • Page 56: System Clock Measurement

    ; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P0.0 ; Measure the Fcpu frequency by oscilloscope. Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC frequency. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 56...

  • Page 57: System Operation Mode

    All inactive P0, P1, T0 Wakeup source P0, P1, Reset Reset EHOSC: External high clock IHRC: Internal high clock (8M RC oscillator) ILRC: Internal low clock (16K RC oscillator at 3V) Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 57...

  • Page 58: System Mode Switching Example

    ; Set CPUM1 = 1. Note: If T0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can wakeup the system backs to the previous operation mode. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 58...
  • Page 59 Example: Switch normal/slow mode to green mode and enable T0 wake-up function with RTC. ; Clear T0 counter. B0BSET FT0ENB ; To enable T0 timer ; Go into green mode B0BCLR FCPUM0 ;To set CPUMx = 10 B0BSET FCPUM1 Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 59...

  • Page 60: Wakeup

    P17W P16W P15W P14W P13W P12W P11W P10W Read/Write After reset Bit[7:0] P10W~P17W: Port 1 wakeup function control bits. 0 = Disable P1n wakeup function. 1 = Enable P1n wakeup function. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 60...

  • Page 61: Interrupt

    INT1 Trigger Interrupt Vector Address (0008H) 4-Bit Enable T0IRQ T0 Time Out Global Interrupt Request Signal Latchs Gating TC1IRQ TC1 Time Out Note: The GIE bit must enable during all interrupt operation. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 61...

  • Page 62: Inten Interrupt Enable Register

    0 = Disable T0 interrupt function. 1 = Enable T0 interrupt function. Bit 6 TC1IEN: TC1 timer interrupt control bit. 0 = Disable TC1 interrupt function. 1 = Enable TC1 interrupt function. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 62...

  • Page 63: Intrq Interrupt Request Register

    0 = Disable global interrupt. 1 = Enable global interrupt. Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE Note: The GIE bit must enable during all interrupt operation. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 63...

  • Page 64: Push, Pop Routine

    Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine executed. START INT_SERVICE START: … INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector … ENDP Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 64...

  • Page 65: Int0 (P0.0) Interrupt Operation

    ; P00IRQ = 0, exit interrupt vector B0BCLR FP00IRQ ; Reset P00IRQ … ; INT0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 65...

  • Page 66: Int1 (P0.1) Interrupt Operation

    ; P01IRQ = 0, exit interrupt vector B0BCLR FP01IRQ ; Reset P01IRQ … ; INT1 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 66...

  • Page 67: T0 Interrupt Operation

    A, #74H B0MOV T0C, A ; Reset T0C. … ; T0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 67...
  • Page 68 ; The time must be longer than 16us. B0BCLR FT0IRQ ; Reset T0IRQ … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 68...

  • Page 69: Tc1 Interrupt Operation

    A, #74H B0MOV TC1C, A ; Reset TC1C. … ; TC1 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 69...

  • Page 70: Multi-Interrupt Operation

    ; Jump to exit of IRQ B0BTS0 FTC1IRQ ; Check TC1IRQ INTTC1 ; Jump to TC1 interrupt service routine INT_EXIT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 70...

  • Page 71: O Port

    ; Set all ports to be output mode. B0MOV P0M, A B0MOV P1M, A B0MOV P5M, A B0BCLR P1M.2 ; Set P1.2 to be input mode. B0BSET P1M.2 ; Set P1.2 to be output mode. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 71...

  • Page 72: I/O Pull Up Register

    Note: P0.2 is input only pin and without pull-up resister. The P0UR.2 keeps “1”. Example: I/O Pull up Register A, #0FFH ; Enable Port0, 1, 5 Pull-up register, B0MOV P0UR, A B0MOV P1UR, A B0MOV P5UR, A Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 72...

  • Page 73: I/O Open-Drain Register

    Example: Disable P1.0 to open-drain mode and output low. A, #0 ; Disable P1.0 open-drain function. B0MOV P1OC, A Note: After disable P1 open-drain function, P1 mode returns to last I/O mode. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 73...

  • Page 74: I/O Port Data Register

    Example: Write one bit data to output port. B0BSET P1.3 ; Set P1.3 and P5.4 to be “1”. B0BSET P5.4 B0BCLR P1.3 ; Set P1.3 and P5.4 to be “0”. B0BCLR P5.4 Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 74...

  • Page 75: Timers

    Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the main routine of the program. Main: A,#5AH ; Clear the watchdog timer. B0MOV WDTR,A … CALL SUB1 CALL SUB2 … … … MAIN Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 75...
  • Page 76 ; I/O and RAM are correct. Clear watchdog timer and ; execute program. B0BSET FWDRST ; Only one clearing watchdog timer of whole program. … CALL SUB1 CALL SUB2 … … … MAIN Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 76...

  • Page 77: Timer 0 (T0)

    The delay is about 16us and use T0 interrupt service routine executing time to be the 16us delay time. 2. In RTC mode, the T0 interval time is fixed at 0.5 sec and T0C is 256 counts. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 77...

  • Page 78: T0M Mode Register

    T0ENB: T0 counter control bit. 0 = Disable T0 timer. 1 = Enable T0 timer. Note: T0RATE is not available in RTC mode. The T0 interval time is fixed at 0.5 sec. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 78...

  • Page 79: T0C Counting Register

    488.281 us Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us Note: In RTC mode, T0C is 256 counts and generatesT0 0.5 sec interval time. Don’t change T0C value in RTC mode. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 79...

  • Page 80: T0 Timer Operation Sequence

    Set T0 interrupt interval time. A,#7FH B0MOV T0C,A ; Set T0C value. Set T0 timer function mode. B0BSET FT0IEN ; Enable T0 interrupt function. Enable T0 timer. B0BSET FT0ENB ; Enable T0 timer. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 80...

  • Page 81: Timer/Counter 0 (Tc1)

    TC1 / 2 P5.3 TC1R Reload ALOAD1, TC1OUT Data Buffer TC1 Rate (Fcpu/2~Fcpu/256) PWM1OUT Compare TC1CKS TC1ENB Fcpu Load TC1C 8-Bit Binary Up TC1 Time Out Counting Counter INT1 (Schmitter Trigger) CPUM0,1 Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 81...

  • Page 82: Tc1M Mode Register

    1 = Enable TC1 timer. Note: When TC1CKS=1, TC1 became an external event counter and TC1RATE is useless. No more P0.1 interrupt request will be raised. (P0.1IRQ will be always 0). Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 82...

  • Page 83: Tc1C Counting Register

    500 ms 1953.125 us Fcpu/8 2.048 ms 8 us 250 ms 976.563 us Fcpu/4 1.024 ms 4 us 125 ms 488.281 us Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 83...

  • Page 84: Tc1R Auto-Load Register

    TC1R initial value = N - (TC1 interrupt interval time * input clock) = 256 - (10ms * 4MHz / 4 / 64) = 256 - (10 * 4 * 10 / 4 / 64) = 100 = 64H Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 84...

  • Page 85: Tc1 Clock Frequency Output (Buzzer)

    ; Enable TC1 output to P5.3 and disable P5.3 I/O function B0BSET FALOAD1 ; Enable TC1 auto-reload function B0BSET FTC1ENB ; Enable TC1 timer Note: Buzzer output is enable, and “PWM1OUT” must be “0”. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 85...

  • Page 86: Tc1 Timer Operation Sequence

    Set TC1 timer function mode. B0BSET FTC1IEN ; Enable TC1 interrupt function. B0BSET FTC1OUT ; Enable TC1OUT (Buzzer) function. B0BSET FPWM1OUT ; Enable PWM function. Enable TC1 timer. B0BSET FTC1ENB ; Enable TC1 timer. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 86...

  • Page 87: Pwm1 Mode

    Overflow per 16 count The Output duty of PWM is with different TC1R. Duty range is from 0/256~255/256. …… …… …… …… TC1 Clock TC1R=00H High TC1R=01H High TC1R=80H High TC1R=FFH Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 87...

  • Page 88: Tc1Irq And Pwm Duty

    PWM duty. TC1 Overflow, TC1IRQ = 1 0xFF TC1C Value 0x00 PWM1 Output (Duty Range 0~255) PWM1 Output (Duty Range 0~63) PWM1 Output (Duty Range 0~31) PWM1 Output (Duty Range 0~15) Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 88...

  • Page 89: Pwm Program Example

    TC1R, A INCMS BUF0 ; Get the new TC1R value from the BUF0 buffer defined by ; programming. B0MOV A, BUF0 B0MOV TC1R, A Note: The PWM can work with interrupt request. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 89...

  • Page 90: Pwm1 Duty Changing Notice

    Above diagram is shown the waveform with fixed TC1R. In every TC1C overflow PWM output “High, when TC1C≧ TC1R PWM output ”Low”. Note: Setting PWM duty in program processing must be at the new cycle start. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 90...
  • Page 91 B0BTS1 FTC1IRQ INT_SER90 B0MOV A, TC1RBUF ; When TC1 Interrupt occurs, update TC1R. B0MOV TC1R, A … … INT_SER90: … ; Pop routine to load ACC and PFLAG from buffers. RETI Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 91...

  • Page 92: Ir Output

    Up Counting Reload Value Output Low IROUT TC0R Reload TC0D Data Buffer Data Buffer IROUT pin Compare IR Signal IROUT Load TC0C TC0C Overflow Fhosc 8-Bit Binary Up Counting Counter CPUM0 Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 92...

  • Page 93: Ir Control Register

    Bit 2 Bit 1 Bit 0 TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0 TC0C Read/Write After reset Note: Set TC0C=TC0R before IR output enable to make sure the first cycle correct. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 93...

  • Page 94: Tc0R Auto-Load Register

    TC0R initial value = 256 - (TC0 interrupt interval time * input clock) TC0 interval time = 1/38KHz = 26.3us Input clock = external oscillator 4MHz. TC0R = 256 - (26.3us * 4MHz) = 150.8 ≈ 151 = 97h Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 94...

  • Page 95: Tc0D Ir Duty Control Register

    1/2 duty 1/3 duty 1/4duty (KHz) Rate 193.50 172.67 162.25 0.00% 200.50 182.00 172.75 0.10% 203.50 186.00 177.25 0.25% 39.2 205.00 188.00 179.50 0.04% 206.00 189.33 181.00 0.00% 220.50 208.67 202.75 0.60% Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 95...

  • Page 96: Ir Output Operation Sequence

    A, #IRDUTYVAL ;TC0D value for IR duty. TC0D, A Enable IR output. BSET FIREN ; Set IROUT pin to IR carry output function. BSET FCREN ; Set IR carry signal output. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 96...

  • Page 97: Analog Comparaotr

    CM1N: Comparator 1 positive input pin shared with P2.5. CM1N enables when CM1EN=1. CM1O: Comparator 1 output pin shared with P2.7. CM1O enables when CM1EN=1 and CM1OEN = 1. The comparator pins are GPIO mode except above conditions. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 97...
  • Page 98 CMnEN = 1, CMnOEN = 0, CMnREF = 0 CMnEN = 1, CMnOEN = 0, CMnREF = 1 Note: The comparator output pin signal is through internal buffer and not pure analog comparator output. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 98...

  • Page 99: Cp0M Register

    1 = CM0P voltage or comparator 0 reference voltage is larger than CM0N voltage. Bit[1:0] CMS[1:0]: Comparator internal reference voltage select bit. 00 = 0.9V, 01 = 1.0V, 10 = 1.1V, 11 = 1.2V Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 99...

  • Page 100: Cp1M Register

    1 = CM1P voltage or comparator 1 reference voltage is larger than CM1N voltage. Note: CMnOUT is comparator raw output without latch. It varies depend on the comparator process result. But the CMnIRQ is latch comparator output result. It must be cleared by program. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 100...

  • Page 101: Analog Comparator Application

    B0BTS1 FCM1IRQ ; Check comparator 1. The CM1IRQ is latch result, so use it ; to determine the comparator result. LowBat ; Is low battery status, go to low battery routine. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 101...
  • Page 102 SN8P26L00 Series 8-Bit Micro-Controller NoBat ; Is no battery status, go to no battery routine. ; Low battery process. LowBat: … … ; No battery process. NoBat: … … Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 102...

  • Page 103: Instruction Table

    Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1. 2. If branch condition is true then “S = 1”, otherwise “S = 0”. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 103...

  • Page 104: Electrical Characteristic

    Low voltage reset level. Fcpu = 1 MHz. LVD Voltage Vdet1 Low voltage indicator level. Fcpu = 1 MHz. Vdet2 Low voltage indicator level. Fcpu = 1 MHz *These parameters are for design reference, not tested. Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 104...

  • Page 105: Otp Programming Pin

    JP1 for MP transition board DIP13 DIP36 DIP14 DIP35 DIP15 DIP34 DIP16 DIP33 DIP17 DIP32 DIP18 DIP31 DIP19 DIP30 DIP20 DIP29 DIP21 DIP28 DIP22 DIP27 DIP23 DIP26 DIP24 DIP25 JP3 for MP transition board Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 105...

  • Page 106: Programming Pin Mapping

    Chip Name SN8P26L34KSX SN8P26L32PS SN8P26L321P/S/X EZ Writer OTP IC / JP3 Pin Assigment Connector Number Name Number Number Number P5.0 P5.0 P5.0 P1.0 P1.0 P1.0 P5.1 P5.1 P5.1 ALSB/PDB P1.1 P1.1 P1.1 Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 106...

  • Page 107: Marking Definition

    Marking Definition 14.1 INTRODUCTION There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit MCU for order or obtain information. This definition is only for Blank OTP MCU. 14.2 MARKING INDETIFICATION SYSTEM SN8 X Part No.

  • Page 108: Marking Example

    9=09 A=10 B=11 ..1=January Month 2=February ..9=September A=October B=November C=December 03= 2003 Year 04= 2004 05= 2005 06= 2006 ..Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 108...

  • Page 109: Package Information

    35.306 35.306 35.560 0.310 7.874 0.283 0.288 0.293 7.188 7.315 7.442 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.330 0.350 0.370 8.382 8.890 9.398 θ° 0° 7° 15° 0° 7° 15° Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 109...

  • Page 110: Sop 28 Pin

    0.697 0.705 0.713 17.704 17.907 18.110 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.325 10.643 0.016 0.033 0.050 0.406 0.838 1.270 θ° 0° 4° 8° 0° 4° 8° Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 110...

  • Page 111: Ssop 28 Pin

    0.40 0.41 7.40 7.80 8.20 0.29 0.31 0.32 5.00 5.30 5.60 0.20 0.21 0.22 0.0259BSC 0.65BSC 0.63 0.90 1.03 0.02 0.04 0.04 0.09 0.00 θ° 0° 4° 8° 0° 4° 8° Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 111...

  • Page 112: P-Dip 18 Pin

    22.352 22.860 23.368 0.300 7.620 0.245 0.250 0.255 6.223 6.350 6.477 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.335 0.355 0.375 8.509 9.017 9.525 θ° 0° 7° 15° 0° 7° 15° Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 112...

  • Page 113: Sop 18 Pin

    0.447 0.455 0.463 11.354 11.557 11.760 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.325 10.643 0.016 0.033 0.050 0.406 0.838 1.270 θ° 0° 4° 8° 0° 4° 8° Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 113...
  • Page 114 24.892 26.162 26.924 0.300 7.620 0.245 0.250 0.255 6.223 6.350 6.477 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.335 0.355 0.375 8.509 9.017 9.525 θ° 0° 7° 15° 0° 7° 15° Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 114...
  • Page 115 0.496 0.502 0.508 12.598 12.751 12.903 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.325 10.643 0.016 0.033 0.050 0.406 0.838 1.270 θ° 0° 4° 8° 0° 4° 8° Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 115...

  • Page 116: Ssop 20 Pin

    3.900 4.000 0.025 0.635 0.010 0.017 0.020 0.250 0.420 0.500 0.016 0.025 0.050 0.400 0.635 1.270 0.039 0.041 0.043 1.000 1.050 1.100 0.059 1.500 0.004 0.100 θ° 0° 8° 0° 8° Preliminary Version 0.2 SONiX TECHNOLOGY CO., LTD Page 116...
  • Page 117 SONIX product could create a situation where personal injury or death may occur.

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