SONIX SN8P2511 User Manual
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SONIX SN8P2511 User Manual

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SN8P2511
USER'S MANUAL
Version 1.2
SN8P2511
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
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8-Bit Micro-Controller
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Version 1.2
SN8P2511

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  • Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.

  • Page 2: Amendent History

    VER 1.0 Feb. 2012 First issue. VER 1.1 Apr. 2012 Add features selection table and migration section. VER 1.2 Jan. 2013 Modify 32KHz oscillator to match capacitor in external high-speed oscillator section. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 2...

  • Page 3: Table Of Contents

    THE SYSTEM OPERATING VOLTAGE ..................32 LOW VOLTAGE DETECTOR (LVD) .................... 32 BROWN OUT RESET IMPROVEMENT ..................34 EXTERNAL RESET ........................35 EXTERNAL RESET CIRCUIT ....................... 35 3.9.1 Simply RC Reset Circuit ......................35 Version 1.2 SONiX TECHNOLOGY CO., LTD Page 3...
  • Page 4 TIMER 0 (T0) ........................... 67 8.2.1 OVERVIEW ..........................67 8.2.2 T0 Timer Operation ........................68 8.2.3 T0M MODE REGISTER ......................69 8.2.4 T0C COUNTING REGISTER ....................69 8.2.5 T0 TIMER OPERATION EXPLAME ..................70 Version 1.2 SONiX TECHNOLOGY CO., LTD Page 4...
  • Page 5 13.3 MARKING EXAMPLE ........................89 13.4 DATECODE SYSTEM ........................89 PACKAGE INFORMATION ......................90 14.1 P-DIP 14 PIN ............................ 90 14.2 SOP 14 PIN ............................91 14.3 SSOP 16 PIN ............................. 92 Version 1.2 SONiX TECHNOLOGY CO., LTD Page 5...

  • Page 6: Product Overview

    No limitation. support Fosc/1 and Fosc/2. SN8P2511 is compatible to SN8P2501B. SN8P2501B code can transfer to SN8P2511 directly. Program the original SN8 of SN8P2501B into SN8P2511 directly with declare SN8P2511 chip name in source code and re-compile again. Version 1.2 SONiX TECHNOLOGY CO., LTD...

  • Page 7: System Block Diagram

    SN8P2511S (SOP 14 pins) P2.2 P2.3 P2.1 P2.4 P2.0 P2.5 P1.3/XIN P0.0/INT0 P1.2/XOUT P1.0 P1.1/RST/VPP P5.4/BZ0/PWM0 SN8P2511P SN8P2511S SN8P2511X (SSOP 16 pins) P2.2 P2.3 P2.1 P2.4 P2.0 P2.5 P1.3/XIN P0.0/INT0 P1.2/XOUT P1.0 P1.1/RST/VPP P5.4/BZ0/PWM0 SN8P2511X Version 1.2 SONiX TECHNOLOGY CO., LTD Page 7...

  • Page 8: Pin Descriptions

    P5.4: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. P5.4/PWM0/BZ0 PWM0: PWM output pin. BZ0: Buzzer TC0/2 output pin. P2 [5:0]: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up P2 [5:0] resisters. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 8...

  • Page 9: Pin Circuit Diagrams

     GPIO structure: Pull-Up Resistor PnUR I/O Input Bus Output I/O Output Bus Latch  Open-drain share pin structure: Pull-Up Resistor PnUR I/O Input Bus P1OC Output I/O Output Bus Latch Open-Drain Version 1.2 SONiX TECHNOLOGY CO., LTD Page 9...

  • Page 10: Central Processor Unit (Cpu)

    The Interrupt vector is the head of interrupt service routine when any interrupt occurring. The General purpose area is main program area including main loop, sub-routines and data table. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 10...

  • Page 11: Reset Vector (0000H)

    Example: Defining Reset Vector ; 0000H START ; Jump to user program address. … START: ; 0010H, The head of user program. … ; User program … ENDP ; End of program Version 1.2 SONiX TECHNOLOGY CO., LTD Page 11...

  • Page 12: Interrupt Vector (0008H)

    RETI ; End of interrupt service routine … START: ; The head of user program. … ; User program … START ; End of user program … ENDP ; End of program Version 1.2 SONiX TECHNOLOGY CO., LTD Page 12...
  • Page 13 ; End of program.  Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.

  • Page 14: Look-Up Table Description

    Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically.  Example: INC_YZ macro. INC_YZ MACRO INCMS ; Z+1 ; Not overflow INCMS ; Y+1 ; Not overflow ENDM Version 1.2 SONiX TECHNOLOGY CO., LTD Page 14...
  • Page 15 ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 … TABLE1: 0035H ; To define a word (16 bits) data. 5105H 2012H … Version 1.2 SONiX TECHNOLOGY CO., LTD Page 15...

  • Page 16: Jump Table Description

    ; ACC = 3, jump to A3POINT SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
  • Page 17 ; ACC = 1, jump to A1POINT 0X0102 A2POINT ; ACC = 2, jump to A2POINT 0X0103 A3POINT ; ACC = 3, jump to A3POINT 0X0104 A4POINT ; ACC = 4, jump to A4POINT Version 1.2 SONiX TECHNOLOGY CO., LTD Page 17...

  • Page 18: Checksum Calculation

    ; If Not jump to checksum calculate CHECKSUM_END ; If Yes checksum calculated is done. Y_ADD_1: INCMS ; Increase Y ; Jump to checksum calculate CHECKSUM_END: … … END_USER_CODE: ; Label of program end Version 1.2 SONiX TECHNOLOGY CO., LTD Page 18...

  • Page 19: Data Memory (Ram)

    System Register “ 0FFh End of Bank 0 The 48-byte general purpose RAM is separated into Bank 0. Sonix provides “Bank 0” type instructions (e.g. b0mov, b0add, b0bts1, b0bset…) to control Bank 0 RAM directly. 2.2.1 SYSTEM REGISTER 2.2.1.1 SYSTEM REGISTER TABLE...

  • Page 20: Bit Definition Of System Register

    All of register names had been declared in SN8ASM assembler. One-bit name had been declared in SN8ASM assembler with “F” prefix code. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 20...

  • Page 21: Accumulator

    “PUSH”, “POP” save and load ACC, PFLAG data into buffers.  Example: Protect ACC and working registers. INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector Version 1.2 SONiX TECHNOLOGY CO., LTD Page 21...

  • Page 22: Program Flag

    1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero.  Note: Refer to instruction set table for detailed information of C, DC and Z flags. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 22...

  • Page 23: Program Counter

    INCS BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: INCMS instruction: INCMS BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: Version 1.2 SONiX TECHNOLOGY CO., LTD Page 23...
  • Page 24 ; If ACC = 0, jump to A0POINT A1POINT ; ACC = 1, jump to A1POINT A2POINT ; ACC = 2, jump to A2POINT A3POINT ; ACC = 3, jump to A3POINT … … Version 1.2 SONiX TECHNOLOGY CO., LTD Page 24...

  • Page 25: Y, Z Registers

    Bit 2 Bit 1 Bit 0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Read/Write After reset  Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 25...

  • Page 26: Addressing Mode

    ; To clear Y register to access RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 26...

  • Page 27: Stack Operation

    1 = Enable. Please refer to the interrupt chapter.  Example: Stack pointer (STKP) reset, we strongly recommended to clear the stack pointers in the beginning of the program. A, #00000011B B0MOV STKP, A Version 1.2 SONiX TECHNOLOGY CO., LTD Page 27...

  • Page 28: Stack Operation Example

    (PC) to the program counter registers. The Stack-Restore operation is as the following table. STKP Register Stack Buffer Stack Level Description STKPB1 STKPB0 High Byte Low Byte STK3H STK3L STK2H STK2L STK1H STK1L STK0H STK0L Free Free Version 1.2 SONiX TECHNOLOGY CO., LTD Page 28...

  • Page 29: Code Option Table

    Fcpu is limited below Fosc/1 and Fosc/2. The fast Fcpu rate is Fosc/4. If noise filter disable, the Fosc/1 and Fosc/2 options are released. In high noisy environment, enable noise filter, enable watchdog timer and select a good LVD level can make whole system work well and avoid error event occurrence. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 29...

  • Page 30: Reset

    High Detect Low Detect Watchdog Overflow Watchdog Normal Run Watchdog Reset Watchdog Stop System Normal Run System Status System Stop Power On External Watchdog Delay Time Reset Delay Reset Delay Time Time Version 1.2 SONiX TECHNOLOGY CO., LTD Page 30...

  • Page 31: Power On Reset

    (e.g. EFT interference or external loading changed). The brown out reset would make the system not work well or executing program error. System Work Well Area System Work Error Area Brown Out Reset Diagram Version 1.2 SONiX TECHNOLOGY CO., LTD Page 31...

  • Page 32: The System Operating Voltage

    The dead-band definition is the system minimum operating voltage above the system reset voltage. 3.6 LOW VOLTAGE DETECTOR (LVD) LVD Detect Voltage Power Power is below LVD Detect Voltage and System Reset. System Normal Run System Status System Stop Power On Delay Time Version 1.2 SONiX TECHNOLOGY CO., LTD Page 32...
  • Page 33 8-Bit Micro-Controller The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by each MCU.

  • Page 34: Brown Out Reset Improvement

    IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead-band. The external reset information is described in the next section. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 34...

  • Page 35: External Reset

    The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference.  Note: The reset circuit is no any protection against unusual power or brown out reset. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 35...

  • Page 36: Diode & Rc Reset Circuit

    PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener specification. Select the right zener voltage to conform the application. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 36...

  • Page 37: Voltage Bias Reset Circuit

    The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can improve all power variation. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 37...

  • Page 38: System Clock

    Fcpu: Instruction cycle. SONIX provides a “Noise Filter” controlled by code option. In high noisy situation, the noise filter can isolate noise outside and protect system works well. The minimum Fcpu of high clock is limited at Fhosc/4 when noise filter enable.

  • Page 39: Noise Filter

    32KHz oscillator is the RTC clock source to supply a accurately real time clock rate. 4.4.1 HIGH_CLK CODE OPTION For difference clock functions, Sonix provides multi-type system high clock options controlled by “High_CLK” code option. The High_CLK code option defines the system oscillator types including IHRC_16M, IHRC_RTC, RC, 32K X’tal, 12M X’tal and 4M X’tal.

  • Page 40: External Oscillator Application Circuit

     Note: Connect the Crystal/Ceramic and C as near as possible to the XIN/XOUT/VSS pins of micro-controller. Connect the R and C as near as possible to the VDD pin of micro-controller. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 40...

  • Page 41: System Low-Speed Clock

    ; oscillator called power down mode (sleep mode).  Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1 (32K, watchdog disable) bits of OSCM register. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 41...

  • Page 42: Oscm Register

    ; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P0.0 ; Measure the Fcpu frequency by oscilloscope.  Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC frequency. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 42...

  • Page 43: System Clock Timing

    External Reset Pin Reset Timing Reset pin falling edge trigger system reset. External Reset Pin Reset pin returns to high status. External Reset Flag Oscillator Tcfg Tost Tosp Fcpu (Instruction Cycle) System is under reset status. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 43...
  • Page 44 Green Mode Wake-up Timing Edge trigger system wake-up. Wake-up Pin Falling Edge Wake-up Pin Rising Edge Timer overflow. Timer 0xFD 0xFE 0xFF 0x00 0x01 0x02 Oscillator Fcpu (Instruction Cycle) System inserts into green mode. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 44...
  • Page 45 The RC type oscillator’s start-up time is faster than crystal type oscillator. RC Oscillator Tost Ceramic/Resonator Tost Crystal Tost Low Speed Crystal (32K, 455K) Tost Version 1.2 SONiX TECHNOLOGY CO., LTD Page 45...

  • Page 46: System Operation Mode

    All active All inactive Wakeup source P0, P1, T0, Reset P0, P1, Reset  EHOSC: External high-speed oscillator (XIN/XOUT).  IHRC: Internal high-speed oscillator RC type.  ILRC: Internal low-speed oscillator RC type. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 46...

  • Page 47: Normal Mode

    Note: If the system is in normal mode, to set STPHX=1 to disable the high clock oscillator. The system is under no system clock condition. This condition makes the system stay as power down mode, and can be wake-up by P0, P1 level change trigger. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 47...

  • Page 48: Green Mode

    PWN and buzzer output functions active in green mode, but the timer can’t wake-up the system as overflow.  Note: Sonix provides “GreenMode” macro to control green mode operation. It is necessary to use “GreenMode” macro to control system inserting green mode.

  • Page 49: Operating Mode Control Macro

    SN8P2511 8-Bit Micro-Controller 5.6 OPERATING MODE CONTROL MACRO Sonix provides operating mode control macros to switch system operating mode easily. Macro Length Description SleepMode 1-word The system insets into Sleep Mode (Power Down Mode). GreenMode 3-word The system inserts into Green Mode.

  • Page 50: Wakeup

    The wakeup time is as the following. The wakeup time = 1/Fhosc *32 = 2 us (Fhosc = 16MHz)  Note: The high clock start-up time is depended on the VDD and oscillator type of high clock. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 50...

  • Page 51: P1W Wakeup Control Register

    Bit 2 Bit 1 Bit 0 P13W P12W P11W P10W Read/Write After reset Bit[3:0] P10W~P13W: Port 1 wakeup function control bits. 0 = Disable P1n wakeup function. 1 = Enable P1n wakeup function. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 51...

  • Page 52: Interrupt

    0 = Disable T0 interrupt function. 1 = Enable T0 interrupt function. Bit 5 TC0IEN: TC0 timer interrupt control bit. 0 = Disable TC0 interrupt function. 1 = Enable TC0 interrupt function. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 52...

  • Page 53: Intrq Interrupt Request Register

    0 = Disable global interrupt. 1 = Enable global interrupt.  Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE  Note: The GIE bit must enable during all interrupt operation. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 53...

  • Page 54: Push, Pop Routine

    Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine executed. START INT_SERVICE START: … INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector … ENDP Version 1.2 SONiX TECHNOLOGY CO., LTD Page 54...

  • Page 55: External Interrupt Operation (Int0)

    ; P00IRQ = 0, exit interrupt vector B0BCLR FP00IRQ ; Reset P00IRQ … ; INT0 interrupt service routine EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.2 SONiX TECHNOLOGY CO., LTD Page 55...

  • Page 56: T0 Interrupt Operation

    A, #64H B0MOV T0C, A ; Reset T0C. … ; T0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.2 SONiX TECHNOLOGY CO., LTD Page 56...
  • Page 57 EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector  Note: We strongly recommend to clear T0IRQ must be used b0bclr or bclr instructions. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 57...

  • Page 58: Tc0 Interrupt Operation

    EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector  Note: We strongly recommend to clear TC0IRQ must be used b0bclr or bclr instructions. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 58...

  • Page 59: Multi-Interrupt Operation

    ; Jump to exit of IRQ B0BTS0 FTC0IRQ ; Check TC0IRQ INTTC0 ; Jump to TC0 interrupt service routine INT_EXIT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.2 SONiX TECHNOLOGY CO., LTD Page 59...

  • Page 60: I/O Port

    High_CLK code option = 32K, 4M, 12M, IHRC_RTC P1.3 High_CLK code option = RC, 32K, 4M, 12M, IHRC_RTC PWM0 TC0ENB=1, PWM0OUT=1 P5.4 TC0ENB=1, TC0OUT=1, PWM0OUT=0 * DC: Digital Characteristic. AC: Analog Characteristic. HV: High Voltage Characteristic. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 60...

  • Page 61: I/O Port Mode

    ; Set all ports to be output mode. B0MOV P0M, A B0MOV P2M,A B0MOV P5M, A B0BCLR P2M.0 ; Set P2.0 to be input mode. B0BSET P2M.0 ; Set P2.0 to be output mode. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 61...

  • Page 62: I/O Pull Up Register

    Note: P1.1 is input only pin and without pull-up resister. The P1UR.1 is undefined.  Example: I/O Pull up Register A, #0FFH ; Enable Port0, 2, 5 Pull-up register, B0MOV P0UR, A B0MOV P2UR,A B0MOV P5UR, A Version 1.2 SONiX TECHNOLOGY CO., LTD Page 62...

  • Page 63: I/O Open-Drain Register

    Example: Disable P1.0 to open-drain mode and output low. A, #0 ; Disable P1.0 open-drain function. B0MOV P1OC, A  Note: After disable P1.0 open-drain function, P1.0 mode returns to last I/O mode. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 63...

  • Page 64: I/O Port Data Register

    Example: Write one bit data to output port. ; Set P2.0 and P1.3 to be “1”. B0BSET P2.0 B0BSET P1.3 ; Set P2.0 and P1.3 to be “0”. B0BCLR P2.0 B0BCLR P1.3 Version 1.2 SONiX TECHNOLOGY CO., LTD Page 64...

  • Page 65: Timers

    ; Clear the watchdog timer. B0MOV WDTR, A … CALL SUB1 CALL SUB2 … MAIN  Example: Clear watchdog timer by “@RST_WDT” macro of Sonix IDE. Main: @RST_WDT ; Clear the watchdog timer. … CALL SUB1 CALL SUB2 … MAIN Version 1.2...
  • Page 66 ; I/O and RAM are correct. Clear watchdog timer and ; execute program. A, #5AH ; Clear the watchdog timer. B0MOV WDTR, A … CALL SUB1 CALL SUB2 … … … MAIN Version 1.2 SONiX TECHNOLOGY CO., LTD Page 66...

  • Page 67: Timer 0 (T0)

    Load T0C Value by Program. T0TB Fcpu T0C 8-Bit Binary Up Counting Counter T0IRQ Interrupt Flag CPUM0,1 (T0 timer overflow.) T0ENB  Note: In RTC mode, don’t reset T0C in interrupt service routine. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 67...

  • Page 68: T0 Timer Operation

    16.384 65.536 001b Fcpu/128 8.192 32.768 010b Fcpu/64 4.096 16.384 011b Fcpu/32 2.048 8.192 100b Fcpu/16 1.024 4.096 101b Fcpu/8 0.512 2.048 110b Fcpu/4 0.256 1.024 111b Fcpu/2 0.128 0.512 32768Hz/64 1.953 Version 1.2 SONiX TECHNOLOGY CO., LTD Page 68...

  • Page 69: T0M Mode Register

    * 4 * 10 / 4 / 128) = B2H  Note: In RTC mode, T0C is 256 counts and generatesT0 0.5 sec interval time. Don’t change T0C value in RTC mode. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 69...

  • Page 70: T0 Timer Operation Explame

    ; Set T0 RTC function. B0BSET FT0TB ; Clear T0C. ; Clear T0IRQ B0BCLR FT0IRQ ; Enable T0 timer and interrupt function. B0BSET FT0IEN ; Enable T0 interrupt function. B0BSET FT0ENB ; Enable T0 timer. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 70...

  • Page 71: Tc0 8-Bit Timer/Counter

    TC0 / 2 P5.4 TC0R Reload ALOAD0, TC0OUT Data Buffer TC0 Rate (Fcpu/2~Fcpu/256) PWM0OUT Compare TC0CKS TC0ENB Fcpu Load TC0C 8-Bit Binary Up TC0 Time Out Counting Counter INT0 (Schmitter Trigger) CPUM0,1 Version 1.2 SONiX TECHNOLOGY CO., LTD Page 71...

  • Page 72: Tc0 Timer Operation

    000b Fcpu/256 16.384 65.536 001b Fcpu/128 8.192 32.768 010b Fcpu/64 4.096 16.384 011b Fcpu/32 2.048 8.192 100b Fcpu/16 1.024 4.096 101b Fcpu/8 0.512 2.048 110b Fcpu/4 0.256 1.024 111b Fcpu/2 0.128 0.512 Version 1.2 SONiX TECHNOLOGY CO., LTD Page 72...

  • Page 73: Tc0M Mode Register

    1 = Enable TC0 timer.  Note: When TC0CKS=1, TC0 became an external event counter and TC0RATE is useless. No more P0.0 interrupt request will be raised. (P0.0IRQ will be always 0). Version 1.2 SONiX TECHNOLOGY CO., LTD Page 73...

  • Page 74: Tc0C Counting Register

    Overflow per 256 count 0x00~0xFF 00000000b~11111111b Overflow per 256 count 0x00~0x3F xx000000b~xx111111b Overflow per 64 count 0x00~0x1F xxx00000b~xxx11111b Overflow per 32 count 0x00~0x0F xxxx0000b~xxxx1111b Overflow per 16 count 0x00~0xFF 00000000b~11111111b Overflow per 256 count Version 1.2 SONiX TECHNOLOGY CO., LTD Page 74...

  • Page 75: Tc0R Auto-Reload Register

    TC0C/TC0R initial value = 256 - (TC0 interval time * input clock) = 256 - (10ms * 4MHz / 4 / 128) = 256 - (10 * 4 * 10 / 4 / 128) = B2H Version 1.2 SONiX TECHNOLOGY CO., LTD Page 75...

  • Page 76: Tc0 Event Counter

    TC0 Timer Interval Time Buzzer Output 0x00 0x00 0x00 TC0C 0xFF 0xFF 0xFF TC0R TC0R TC0R TC0IRQ TC0IRQ is cleared by program. TC0 timer overflows. TC0IRQ set as “1”. Reload TC0C from TC0R automatically. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 76...

  • Page 77: Pulse Width Modulation (Pwm)

    PWM exchanges to low status. PWM outputs high status. PWM exchanges to high status. TC0R TC0R 0x00 0x01 0x02 TC0R 0xFD 0xFE 0xFF 0x00 0x01 0x02 TC0C PWM Output One complete cycle of PWM. Next cycle. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 77...
  • Page 78 GPIO mode (output high). High impendence (floating) PWM Output PWM0OUT=0. PWM0OUT=1. PWM0OUT=1. The pin exchanges to output PWM0OUT=0. The pin exchanges mode and outputs PWM signal automatically. to last GPIO mode (input). Version 1.2 SONiX TECHNOLOGY CO., LTD Page 78...

  • Page 79: Tc0 Timer Operation Explame

    ; TC0C must be equal to TC0R. B0MOV TC0C, A B0MOV TC0R, A ; Clear TC0IRQ B0BCLR FTC0IRQ ; Enable TC0 timer and interrupt function. B0BSET FTC0IEN ; Enable TC0 interrupt function. B0BSET FTC0ENB ; Enable TC0 timer. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 79...
  • Page 80 ; Set TC0R register for PWM duty. A, #value B0MOV TC0R, A ; Clear TC0C as initial value. TC0C ; Enable PWM and TC0 timer. B0BSET FTC0ENB ; Enable TC0 timer. B0BSET FPWM0OUT ; Enable PWM. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 80...

  • Page 81: Instruction Table

    Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1. 2. If branch condition is true then “S = 1”, otherwise “S = 0”. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 81...

  • Page 82: Electrical Characteristic

    Low voltage reset/indicator level. Fcpu = 1 MHz, Vdet2 0C ~ + 70C External oscillator (32KHz) Capacitor selection for crystal oscillator in 32KHz match capacitor “ ” These parameters are for design reference, not tested. Version 1.2 SONiX TECHNOLOGY CO., LTD Page 82...

  • Page 83: Characteristic Graphs

    The Graphs in this section are for design guidance, not tested or guaranteed. In some graphs, the data presented are outside specified operating range. This is for information only and devices are guaranteed to operate properly only within the specified range (0℃~+70℃ curves are for design reference). Version 1.2 SONiX TECHNOLOGY CO., LTD Page 83...

  • Page 84: Development Tool

    Writer: MPIII writer.  Writer transition board: SN8P2511. 11.1 SN8P2511/2501A/B/C EV-KIT SONIX provides SN8P2511 MCU which includes PWM analog function. The EV-KIT provides LVD configuration to emulation. To emulate the function must be through EV-KIT. SN8P2511/2501A/B/C EV-KIT PCB Outline: ...

  • Page 85: Ice And Ev-Kit Application Notic

    SN8P2511/2501A/B/C EV-KIT schematic: 11.2 ICE AND EV-KIT APPLICATION NOTIC 1. SN8ICE2K Plus II power switch must be turned off before you connect the SN8P2511/2501A/B/C EV-KIT to SN8ICE2K Plus II. 2. Connect EV-KIT JP6/CON1 to ICE JP3/CON1. 3. Turn on SN8ICE2K Plus 2 power switch to start emulation.

  • Page 86: Otp Programming Pin

    JP1 for Writer transition board DIP13 DIP36 JP2 for dice and >48 pin package DIP14 DIP35 DIP15 DIP34 DIP16 DIP33 DIP17 DIP32 DIP18 DIP31 DIP19 DIP30 DIP20 DIP29 DIP21 DIP28 DIP22 DIP27 DIP23 DIP26 DIP24 DIP25 Version 1.2 SONiX TECHNOLOGY CO., LTD Page 86...

  • Page 87: Programming Pin Mapping

    SN8P2511 8-Bit Micro-Controller 12.2 PROGRAMMING PIN MAPPING: Programming Pin Information of SN8P2511 Chip Name SN8P2511P/S(DIP/SOP) SN8P2511X(SSOP) Writer Connector IC and JP3 48-pin text tool Pin Assignment JP1/JP2 JP1/JP2 Pin Number Pin Name Pin Number Pin Name Pin Number Pin Number...

  • Page 88: Marking Definition

    Marking Definition 13.1 INTRODUCTION There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit MCU for order or obtain information. This definition is only for Blank OTP MCU. 13.2 MARKING INDETIFICATION SYSTEM SN8 X PART No.

  • Page 89: Marking Example

    ..9=09 A=10 B=11 ..1=January Month 2=February ..9=September A=October B=November C=December 03= 2003 Year 04= 2004 05= 2005 06= 2006 ..Version 1.2 SONiX TECHNOLOGY CO., LTD Page 89...

  • Page 90: Package Information

    0.775 18.669 1.905 19.685 0.300 7.62 0.245 0.250 0.255 6.223 6.35 6.477 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.335 0.355 0.375 8.509 9.017 9.525 θ° 0° 7° 15° 0° 7° 15° Version 1.2 SONiX TECHNOLOGY CO., LTD Page 90...

  • Page 91: Sop 14 Pin

    0.2490 0.336 0.341 0.344 8.5344 8.6614 8.7376 0.150 0.154 0.157 3.81 3.9116 3.9878 0.050 1.27 0.228 0.236 0.244 5.7912 5.9944 6.1976 0.015 0.025 0.050 0.381 0.635 1.27 θ° 0° 8° 0° 8° Version 1.2 SONiX TECHNOLOGY CO., LTD Page 91...

  • Page 92: Ssop 16 Pin

    0.010 0.1778 0.254 0.007 0.009 0.1778 0.2286 0.189 0.197 4.8006 5.0038 0.150 0.157 3.81 3.9878 0.228 0.244 5.7912 6.1976 0.016 0.050 0.4064 1.27 0.025 BASIC 0.635 BASIC θ° 0° 8° 0° 8° Version 1.2 SONiX TECHNOLOGY CO., LTD Page 92...
  • Page 93 SONIX product could create a situation where personal injury or death may occur.

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