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SONIX SN8P1829 User Manual

8-bit mcu build-in 12-bit adc + pgia + charge-pump regulator + 128 dots lcd driver
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SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SN8P1829
USER'S MANUAL
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
Version 1.0
SONiX TECHNOLOGY CO., LTD

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Summary of Contents for SONIX SN8P1829

  • Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.

  • Page 2: Amendment History

    Feb. 2005 1. “B0MOV M, I”, M only supports 0x80~0x87 2. Add external low clock diagram, Figure7-5,7-6 3. Add note for PUSH/POP only one level. 4. External Reset circuit needs 100-ohm resistance. Figure 6-3, 6-4 Version 1.0 SONiX TECHNOLOGY CO., LTD...

  • Page 3: Table Of Contents

    ADDRESS SPACES ......................13 PROGRAM MEMORY (ROM)..................... 13 DATA MEMORY (RAM) ......................21 WORKING REGISTERS......................23 PROGRAM FLAG ........................26 ACCUMULATOR ........................27 STACK OPERATIONS........................ 28 PROGRAM COUNTER....................... 31 ADDRESSING MODE...................... 34 OVERVIEW..........................34 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 3...
  • Page 4 BASIC TIMER 0 (T0) ........................55 TIMER COUNTER 0 (TC0) ......................56 TIMER COUNTER 1 (TC1) ......................67 PWM FUNCTION DESCRIPTION ....................76 INTERRUPT........................80 OVERVIEW..........................80 INTEN INTERRUPT ENABLE REGISTER ................. 81 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 4...
  • Page 5 I/O PORT DATA REGISTER ....................109 LCD DRIVER....................... 110 LCDM1 REGISTER ........................110 LCD TIMING ..........................112 LCD RAM LOCATION ......................114 3-CHANNEL ADC WITH BATTERY MONITOR ..........115 OVERVIEW..........................115 ADM REGISTER........................116 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 5...
  • Page 6 APPLICATION CIRCUIT..................126 ................126 LOOD RESSURE ETER PPLICATION IRCUIT INSTRUCTION SET TABLE ................127 ELECTRICAL CHARACTERISTIC ..............128 ABSOLUTE MAXIMUM RATING ....................128 ELECTRICAL CHARACTERISTIC ................... 128 PACKAGE INFORMATION ................130 LQFP80............................. 130 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 6...

  • Page 7: Product Overview

    Support hardware multiplier (MUL). FEATURES TABLE Timer Wakeup CHIP Stack LCD Package Buzzer Pin no. T0 TC0 TC1 SN8P1829 8K*16 512*8 4*32 V V 20 12-bit LQFP80 Table 1-1 Selection table of SN8P1829 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 7...

  • Page 8: System Block Diagram

    TIMER & COUNTER TIMER & COUNTER SIO TX/RX SIO TX/RX SIO TX/RX PORT 0 PORT 0 PORT 2 PORT 2 PORT 5 PORT 5 PORT 1 PORT 1 Figure 1-1 Simplified system block diagram Version 1.0 SONiX TECHNOLOGY CO., LTD Page 8...

  • Page 9: Pin Assignment

    OP2OUT 18 43 SEG25/P2.1 P0.0/INT0 19 42 SEG26/P2.2 P0.1/INT1 20 41 SEG27/P2.3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 9...

  • Page 10: Pin Descriptions

    PGIAIN+, PGIAIN- PGIA Input Channels PGIAOUT PGIA Output Channel PGIABIAS PGIA Bias Voltage input Positive capacitor terminal for charge pump regulator Negative capacitor terminal for charge pump regulator Table 1-2 SN8P1829 pin description Version 1.0 SONiX TECHNOLOGY CO., LTD Page 10...

  • Page 11: Pin Circuit Diagrams

    PnM, PnUR PnM, PnUR Latch Latch Int. bus Int. bus Port2 structure Port2 structure P2UR P2UR Int. bus Int. bus LCD wave form LCD wave form P2SEG P2SEG Figure 1-2. Pin Circuit Diagram Version 1.0 SONiX TECHNOLOGY CO., LTD Page 11...

  • Page 12: Code Option Table

    Enable Low Power function to save Operating current Low Power Disable Disable Low Power function Table 2-1. Code Option Table of SN8P1829 Notice: In high noisy environment, enable “Noise Filter”, and disable “Low Power” is strongly recommended. The side effect is to increase the lowest valid working voltage level if enable “Noise Filter” or “Low Power”...

  • Page 13: Address Spaces

    PROGRAM MEMORY (ROM) OVERVIEW ROM Maps for SN8P1829 devices provide 8K x 16 OTP memory that programmable by user. The SN8P1829 program memory is able to fetch instructions through 13-bit wide PC (Program Counter) and can look up ROM data by using ROM code registers (R, X, Y, Z).
  • Page 14 ; Pop 80H ~ 87H system registers B0XCH A, ACCBUF RETI ; End of interrupt service routine START: ; The head of user program. ; User program ; End of user program START ENDP ; End of program Version 1.0 SONiX TECHNOLOGY CO., LTD Page 14...
  • Page 15 ENDP ; End of program Remark: it is easy to get the rules of SONiX program from demo programs given above. These points are as following. 1. The address 0000H is a “JMP” instruction to make the program go to general-purpose ROM area. The 0004H~0007H are reserved.
  • Page 16 ;if Not return to checksum calculate INCMS ;if Yes, increase 4 to Z INCMS INCMS INCMS ;set YZ=0008H then return Y_ADD_1: INCMS ;increase Y ;jump to checksum calculate CHECKSUM_END: ………. ………. END_USER_CODE: ; Label of program end Version 1.0 SONiX TECHNOLOGY CO., LTD Page 16...
  • Page 17 The 8174-word at ROM locations 0010H~1FFEH is used as general-purpose memory. The area stored instruction’s op-code and look-up table data. The SN8P1829 includes jump table function by using program counter (PC) and look-up table function by using ROM code registers (R, X, Y, Z).
  • Page 18 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 TABLE1: 0035H ; To define a word (16 bits) data. 5105H ; “ 2012H ; “ Version 1.0 SONiX TECHNOLOGY CO., LTD Page 18...
  • Page 19 When carry flag occurs after executing of “ADD PCL, A”, it will not affect PCH register. Users have to check if the jump table leaps over the ROM page boundary or the listing file generated by SONiX assembler. If the jump table leaps over the ROM page boundary (e.g.
  • Page 20 SN8P1829 8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”. B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A ; The number of the jump table listing is five.

  • Page 21: Data Memory (Ram)

    8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver DATA MEMORY (RAM) OVERVIEW The SN8P1829 has internally built-in data memory up to 512 bytes for storing general-purpose data and featured with LCD memory space up to 128 locations (4*32 bits) for displaying. 512 * 8-bit general purpose area...
  • Page 22 A, #0FFH ; Set all pins of P1 to be logic high. B0MOV P1, A B0MOV A, P0 ; Read P0 data and store into BUF1 of RAM bank 1. BUF1, A Version 1.0 SONiX TECHNOLOGY CO., LTD Page 22...

  • Page 23: Working Registers

    ; Clear @HL to be zero DECMS L ; L – 1, if L = 0, finish the routine CLR_HL_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 23...
  • Page 24 ; Clear @YZ to be zero DECMS Z ; Y – 1, if Y= 0, finish the routine CLR_YZ_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 24...
  • Page 25 ROM address will stores in R register and the low-byte data in ACC. R initial value = 0000 0000 082H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 25...

  • Page 26: Program Flag

    DC = 0: If executed arithmetic addition without occurring carry signal from low nibble or executed arithmetic subtraction with borrow signal from high nibble. ZERO FLAG Z = 1: After operation, the content of ACC is zero. Z = 0: After operation, the content of ACC is not zero. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 26...

  • Page 27: Accumulator

    B0XCH A, ACCBUF ; Re-load ACC RETI ; Exit interrupt service vector Notice: To save and re-load ACC data must be used “B0XCH” instruction, or the PFLAG value maybe modified by ACC. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 27...

  • Page 28: Stack Operations

    OVERVIEW The stack buffer of SN8P1829 has 8-level high area and each level is 12-bit length. This buffer is designed to save and restore program counter (PC) data when interrupt service executes. The STKP register is designed to point active level to save or restore data from stack buffer for kernel circuit.
  • Page 29 SnPC3 SnPC2 SnPC1 SnPC0 H: Store PCH data as interrupt or call executing. The n expressed 0 ~7. L: Store PCL data as interrupt or call executing. The n expressed 0 ~7. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 29...
  • Page 30 High Byte Low Byte STK7H STK7L STK6H STK6L STK5H STK5L STK4H STK4L STK3H STK3L STK2H STK2L STK1H STK1L STK0H STK0L Table 3-2. STKP, STK H and STK L relative of Stack-Restore Operation Version 1.0 SONiX TECHNOLOGY CO., LTD Page 30...

  • Page 31: Program Counter

    Bit 2 Bit 1 Bit 0 PC12 PC11 PC10 PCL Initial value = 0000 0000 0CEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 31...
  • Page 32 ; Skip next instruction, if BUF0 = 0XFFH. C0STEP ; Else jump to C0STEP. C0STEP: NOP DECMS instruction: DECMS BUF0 ; Skip next instruction, if BUF0 = 0XFFH. C0STEP ; Else jump to C0STEP. C0STEP: NOP Version 1.0 SONiX TECHNOLOGY CO., LTD Page 32...
  • Page 33 ; If ACC = 0, jump to A0POINT JMP A1POINT ; ACC = 1, jump to A1POINT JMP A2POINT ; ACC = 2, jump to A2POINT JMP A3POINT ; ACC = 3, jump to A3POINT Version 1.0 SONiX TECHNOLOGY CO., LTD Page 33...

  • Page 34: Addressing Mode

    8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver ADDRESSING MODE OVERVIEW The SN8P1829 provides three addressing modes to access RAM data, including immediate addressing mode, directly addressing mode and indirectly address mode. The main purpose of the three different modes is described in the following:...
  • Page 35 ; To set Y = 15 for accessing RAM bank 15. B0MOV Z,#12H ; To set an immediate data 12H into Z register. B0MOV A,@YZ ; Use data pointer @YZ reads a data from RAM location 012H into ACC. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 35...

  • Page 36: System Register

    P2UR P5UR @HL @YZ F STK7 STK7 STK6 STK6 STK5 STK5 STK4 STK4 STK3 STK3 STK2 STK2 STK1 STK1 STK0 STK0 Table 5-1. RAM register arrangement of SN8P1829 Description L, H = Working & @HL addressing register Working register and ROM look-up data buffer...
  • Page 37 P22R P21R P20R P2UR 0E5H P54R P53R P52R P51R P50R P5UR 0E6H @HL7 @HL6 @HL5 @HL4 @HL3 @HL2 @HL1 @HL0 0E7H @YZ7 @YZ6 @YZ5 @YZ4 @YZ3 @YZ2 @YZ1 @YZ0 (To be continued) Version 1.0 SONiX TECHNOLOGY CO., LTD Page 37...
  • Page 38 The low nibble of ADR register is read only. e). “b0bset”, “b0bclr”, ”bset”, ”bclr” of instructions just only support “R/W” registers. f). For detail description please refer file of “System Register Quick Reference Table” Version 1.0 SONiX TECHNOLOGY CO., LTD Page 38...

  • Page 39: Power On Reset

    OVERVIEW SN8P1829 provides two system resets. One is external reset and the other is low voltage detector (LVD). The external reset is a simple RC circuit connecting to the reset pin. The low voltage detector (LVD) is built in internal circuit. When one of the reset devices occurs, the system will reset and the system registers become initial value.

  • Page 40: External Reset Description

    Users must to be sure the VDD stable earlier than external reset (Figure 6-2) or the external reset will fail. The external reset circuit is a simple RC circuit as following. 100 ohm 0.1uF Figure 6-3. External Reset Circuit Note: Please connect a 100-ohm resistance in Reset pin. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 40...

  • Page 41: Low Voltage Detector (Lvd) Description

    Users can turn on it for special application like worse power condition. LVD work with external reset function. They are OR active. LVD Detect Level System Reset End of LVD Reset Figure 6-5. LVD Timing Diagram Note: LVD is always Enable in SN8P1829 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 41...

  • Page 42: Oscillators

    OSCILLATORS OVERVIEW The SN8P1829 highly performs the dual clock micro-controller system. The dual clocks are high-speed clock and low-speed clock. The high-speed clock frequency is supplied through the external oscillator circuit. The low-speed clock frequency is supplied through external low clock oscillator (32.768K) by crystal or RC mode. Because Real-Time-Clock (RTC) used low-speed clock for timer, 32768Hz X’tal usually used for low-speed clock to an...
  • Page 43 RTCM [1:0] : Real time clock mode setting bits. There are 4 types RTC timing, 0.5/1/2/4 second. RTCM1 RTCM0 RTC Time (Second) Note: Bit T0TB control T0 as normal timer or Real Time clock. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 43...
  • Page 44 OSCILLATOR DEVIDE BY 2 CODE OPTION SN8P1829 has an external clock divide by 2 function. It is a code option called “High_Clk / 2”. If “High_Clk / 2” is enabled, the external clock frequency is divided by 8 for the F is equal to Fosc/8.
  • Page 45 8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver SYSTEM OSCILLATOR CIRCUITS 20PF CRYSTAL XOUT 20PF Figure 7-2. Crystal/Ceramic Oscillator XOUT Figure 7-3. RC Oscillator External Clock Input XOUT Figure 7-4. External High clock input Version 1.0 SONiX TECHNOLOGY CO., LTD Page 45...
  • Page 46 Note3: In RC type oscillator code option situation, the external clock’s frequency is divided by 2. Note4: The power and ground of external oscillator circuit must be connected from the micro-controller’s VDD and VSS. It is necessary to step up the performance of the whole system. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 46...
  • Page 47 ; Set P1.0 to be output mode for outputting F toggle signal. B0BSET P1.0 ; Output F toggle signal in low-speed clock mode. B0BCLR P1.0 ; Measure the F frequency by oscilloscope. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 47...

  • Page 48: System Mode Description

    To set CUPM0 = 1, the system gets into power down mode. The external high-speed and low-speed oscillators are turned off. The system can be waked up by P0, P1 trigger signal. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 48...

  • Page 49: System Mode Control

    T0, TC0 time out. T0, TC0 time out. External reset circuit active. External reset circuit active. Green Mode Green Mode External reset circuit active. External reset circuit active. Figure 7-7. SN8P1829 System Mode Block Diagram MODE NORMAL SLOW Green SLEEP REMARK HX osc.
  • Page 50 ; To enable T0 timer ; Go into green mode B0BCLR FCPUM0 ;To set CPUM = 10 B0BSET FCPUM1 Note: If T0ENB = 0, T0 is without wakeup from green mode to normal/slow mode function. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 50...

  • Page 51: Wakeup Time

    There are two conditions need wakeup time. One is power down mode to normal mode. The other one is slow mode to normal mode. For the first case, SN8P1829 provides 2048 oscillator clocks to be the wakeup time. However, in the last case, users need to make the wakeup time by themselves.
  • Page 52 SN8P1829 8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver EXTERNAL WAKEUP TRIGGER CONTROL In the SN8P1829, the wakeup trigger direction is control by PEDGE register. PEDGE initial value = 0xx0 0xxx 0BFH Bit 7...

  • Page 53: Timers Counters

    1 / (F =32768Hz ÷ 2 ÷ 16) = 500 ms, F 1 / (F =32768Hz 1 / (32768 ÷ 512 ÷ 16) ~ 0.25s Table 8-1. Watchdog timer overflow time table Version 1.0 SONiX TECHNOLOGY CO., LTD Page 53...
  • Page 54 Example: An operation of watchdog timer is as following. To clear the watchdog timer’s counter in the top of the main routine of the program. Main: B0BSET FWDRST ; Clear the watchdog timer’s counter. CALL SUB1 CALL SUB2 MAIN Version 1.0 SONiX TECHNOLOGY CO., LTD Page 54...

  • Page 55: Basic Timer 0 (T0)

    0 = Timer 0 function as a normal timer system. 1 = Timer 0 function as a Real-Time Clock. The clock source of timer 0 will be switched to external low clock (32.768K crystal oscillator). Version 1.0 SONiX TECHNOLOGY CO., LTD Page 55...

  • Page 56: Timer Counter 0 (Tc0)

    8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock frequency. Arbitrary frequency output (Buzzer output): Outputs selectable clock frequencies to the BZ0 pin (P5.4). PWM function: PWM output can be generated by the PWM1OUT bit and output to PWM0OUT pin (P5.4). Version 1.0 SONiX TECHNOLOGY CO., LTD Page 56...
  • Page 57 1 = To enable the PWM output (The TC0OUT control bit must = 0 ) Note: When TC0CKS=1, TC0 became an external event counter. No more P0.0 interrupt request will be raised. (P00IRQ will be always 0) Version 1.0 SONiX TECHNOLOGY CO., LTD Page 57...
  • Page 58 TC0C initial value = 64 - (TC0 interrupt interval time * input clock) = 64 - (1ms * 3.58 * 10 / 4 / 64) = 64 - (1 * 3.58 * 10 / 4 / 64) = 64-14 = 32H Version 1.0 SONiX TECHNOLOGY CO., LTD Page 58...
  • Page 59 62.5 ms 3.9 ms 0.285 ms 17.9us 31.25 ms 1.95 ms 0.143 ms 8.94us 15.63 ms 0.98 ms 71.25 us 4.47us 7.81 ms 0.49 ms 35.63 us 2.23us 3.91 ms 0.24 ms Version 1.0 SONiX TECHNOLOGY CO., LTD Page 59...
  • Page 60 0.244 ms 17.875 us 1.117us 1.953 ms 0.122 ms 8.936 us 0.587us 0.976 ms 0.061 ms 4.468 us 0.279us 0.488 ms 0.03 ms Table 8-2. The Timing Table of Timer Count TC0 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 60...
  • Page 61 Which N is determinate by code option: TC0_Counter TC0_Counter Max. TC0R value 8-bit 6-bit 5-bit 4-bit Note: TheTC0R must small or equal than Max. TC0R value. Note: The TC0R is write-only register can’t be process by INCMS, DECMS instructions. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 61...
  • Page 62 ; To set TC0R auto-reload register B0BSET FTC0IEN ; To enable TC0 interrupt service B0BCLR FTC0IRQ ; To clear TC0 interrupt request B0BSET FTC0ENB ; To enable TC0 timer B0BSET ALOAD0 ; To enable TC0 auto-reload function. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 62...
  • Page 63 ; TC0 interrupt service routine EXIT_INT ; End of TC0 interrupt service routine and exit interrupt vector EXIT_INT: B0MOV A, PFLAGBUF B0MOV PFLAG, A B0XCH A, ACCBUF ; Restore ACC value. RETI ; Exit interrupt vector Version 1.0 SONiX TECHNOLOGY CO., LTD Page 63...
  • Page 64 ; Set the auto-reload reference value B0MOV TC0C,A B0MOV TC0R,A B0BSET FTC0OUT ; Enable TC0 output to P5.4 and disable P5.4 I/O function B0BSET FALOAD0 ; Enable TC0 auto-reload function B0BSET FTC0ENB ; Enable TC0 timer Version 1.0 SONiX TECHNOLOGY CO., LTD Page 64...
  • Page 65 0.4195 0.6720 1.6892 0.3064 0.4223 0.6793 1.7361 0.3079 0.4252 0.6868 1.7857 0.3094 0.4281 0.6944 1.8382 0.3109 0.4310 0.7022 1.8939 Table 8-3. TC0OUT Frequency Table for F = 4MHz, TC0 Rate = F Version 1.0 SONiX TECHNOLOGY CO., LTD Page 65...
  • Page 66 1.6779 2.6882 6.7568 1.2255 1.6892 2.7174 6.9444 1.2315 1.7007 2.7473 7.1429 1.2376 1.7123 2.7778 7.3529 1.2438 1.7241 2.8090 7.5758 Table 8-4. TC0OUT Frequency Table for F = 16MHz, TC0 Rate = Fcpu/8 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 66...

  • Page 67: Timer Counter 1 (Tc1)

    8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock frequency. Arbitrary frequency output (Buzzer output): Outputs selectable clock frequencies to the BZ1 pin (P5.3). PWM function: PWM output can be generated by the PWM1OUT bit and output to PWM1OUT pin (P5.3). Version 1.0 SONiX TECHNOLOGY CO., LTD Page 67...
  • Page 68 1 = To enable the PWM output (The TC1OUT control bit must = 0 ) Note: Note: When TC1CKS=1, TC1 became an external event counter. No more P0.1 interrupt request will be raised. (P01IRQ will be always 0) Version 1.0 SONiX TECHNOLOGY CO., LTD Page 68...
  • Page 69 TC1C initial value = 64 - (TC0 interrupt interval time * input clock) = 64 - (1ms * 3.58 * 10 / 4 / 64) = 64 - (1 * 3.58 * 10 / 4 / 64) = 64-14 = 32H Version 1.0 SONiX TECHNOLOGY CO., LTD Page 69...
  • Page 70 62.5 ms 3.9 ms 0.285 ms 17.9us 31.25 ms 1.95 ms 0.143 ms 8.94us 15.63 ms 0.98 ms 71.25 us 4.47us 7.81 ms 0.49 ms 35.63 us 2.23us 3.91 ms 0.24 ms Version 1.0 SONiX TECHNOLOGY CO., LTD Page 70...
  • Page 71 0.244 ms 17.875 us 1.117us 1.953 ms 0.122 ms 8.936 us 0.587us 0.976 ms 0.061 ms 4.468 us 0.279us 0.488 ms 0.03 ms Table 8-5. The Timing Table of Timer Count TC1 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 71...
  • Page 72 Which N is determinate by code option: TC1_Counter TC0_Counter Max. TC0R value 8-bit 6-bit 5-bit 4-bit Note: TheTC1R must small or equal than Max. TC1R value. Note: The TC1R is write-only register can’t be process by INCMS, DECMS instructions. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 72...
  • Page 73 ; To set TC1R auto-reload register B0BSET FTC1IEN ; To enable TC1 interrupt service B0BCLR FTC1IRQ ; To clear TC1 interrupt request B0BSET FTC1ENB ; To enable TC1 timer B0BSET ALOAD1 ; To enable TC1 auto-reload function. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 73...
  • Page 74 ; TC1 interrupt service routine EXIT_INT ; End of TC1 interrupt service routine and exit interrupt vector EXIT_INT: B0MOV A, PFLAGBUF B0MOV PFLAG, A B0XCH A, ACCBUF ; Restore ACC value. RETI ; Exit interrupt vector Version 1.0 SONiX TECHNOLOGY CO., LTD Page 74...
  • Page 75 ; Set the auto-reload reference value B0MOV TC1C,A B0MOV TC1R,A B0BSET FTC1OUT ; Enable TC1 output to P5.3 and disable P5.3 I/O function B0BSET FALOAD1 ; Enable TC1 auto-reload function B0BSET FTC1ENB ; Enable TC1 timer Version 1.0 SONiX TECHNOLOGY CO., LTD Page 75...

  • Page 76: Pwm Function Description

    1Fh to 20h 0/32 ~ 31/32 125K Overflow per 32 count 4-bit 0Fh to 10h 0/16 ~ 15/16 250K Overflow per 16 count Table 8-2. The Maximum PWM Frequency Example (TC0RATE/TC1RATE = 111) Version 1.0 SONiX TECHNOLOGY CO., LTD Page 76...
  • Page 77 62/256 62/64 0011 1111 63/256 63/64 0100 0000 64/256. … … 1111 1110 254/256 1111 1111 255/256 Table 8-3. The PWM Duty Cycle Table Note: Functionality is not guaranteed in shaded area. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 77...
  • Page 78 TC0R = 01H TC0_count:5-bit TC0_count:5-bit High High TC0R = 01H TC0R = 01H TC0_count:6-bit TC0_count:6-bit High High TC0R = 01H TC0R = 01H TC0_count:8-bit TC0_count:8-bit Figure 8-6 The Output of PWM with different TC0_Count Version 1.0 SONiX TECHNOLOGY CO., LTD Page 78...
  • Page 79 PWM1 duty modified. It protects the PWM1 signal no glitch as PWM1 duty changing. Note3: The TC0OUT function must be set “0” when PWM0 output enable. The TC1OUT function must be set “0” when PWM1 output enable. Note4: The PWM can work with interrupt request. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 79...

  • Page 80: Interrupt

    INTERRUPT OVERVIEW The SN8P1829 provides 6 interrupt sources, including four internal interrupts (T0, TC0, TC1 & SIO) and two external interrupts (INT0 ~ INT1). These external interrupts can wakeup the chip from power down mode to high-speed normal mode. The external clock input pins of INT0/INT1 are shared with P0.0/P0.1 pins. Once interrupt service is executed, the GIE bit in STKP register will clear to “0”...

  • Page 81: Inten Interrupt Enable Register

    As the result, the system will execute the interrupt vector (ORG 8). If the related bit of INTEN = 0, moreover, the system won’t execute interrupt vector even when the related bit of INTRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 81...

  • Page 82: Interrupt Operation Description

    8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver INTERRUPT OPERATION DESCRIPTION SN8P1829 provides 6 interrupts. The operation of the 6 interrupts is as following. GIE GLOBAL INTERRUPT OPERATION GIE is the global interrupt control bit. All interrupts start work after the GIE = 1. It is necessary for interrupt service request.
  • Page 83 8). If the P00IEN = 0 and the trigger event P00IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even when the P00IRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 83...
  • Page 84 ; P01IRQ = 0, exit interrupt vector B0BCLR FP01IRQ ; Reset P01IRQ ; INT1 interrupt service routine EXIT_INT: ; Pop B0XCH A, ACCBUF ; Restore ACC value. RETI ; Exit interrupt vector Version 1.0 SONiX TECHNOLOGY CO., LTD Page 84...
  • Page 85 FT0IRQ ; Reset T0IRQ A, #74H B0MOV T0C, A ; Reset T0C. ; T0 interrupt service routine EXIT_INT: ; Pop B0XCH A, ACCBUF ; Restore ACC value. RETI ; Exit interrupt vector Version 1.0 SONiX TECHNOLOGY CO., LTD Page 85...
  • Page 86 FTC0IRQ ; Reset TC0IRQ A, #74H B0MOV TC0C, A ; Reset TC0C. ; TC0 interrupt service routine EXIT_INT: ; Pop B0XCH A, ACCBUF ; Restore ACC value. RETI ; Exit interrupt vector Version 1.0 SONiX TECHNOLOGY CO., LTD Page 86...
  • Page 87 FTC1IRQ ; Reset TC1IRQ A, #74H B0MOV TC1C, A ; Reset TC1C. ; TC1 interrupt service routine EXIT_INT: ; Pop B0XCH A, ACCBUF ; Restore ACC value. RETI ; Exit interrupt vector Version 1.0 SONiX TECHNOLOGY CO., LTD Page 87...
  • Page 88 ; SIOIRQ = 0, exit interrupt vector B0BCLR FSIOIRQ ; Reset SIOIRQ ; SIO interrupt service routine EXIT_INT: ; Pop B0XCH A, ACCBUF ; Restore ACC value. RETI ; Exit interrupt vector Version 1.0 SONiX TECHNOLOGY CO., LTD Page 88...
  • Page 89 IEN and IRQ flags to decide executing interrupt service routine or not. Users have to check interrupt control bit and interrupt request flag in interrupt vector. There is a simple routine as following. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 89...
  • Page 90 ; Jump to exit of IRQ B0BTS0 FSIOIRQ ; Check SIOIRQ INTSIO ; Jump to SIO interrupt service routine INT_EXIT: ; Pop B0XCH A, ACCBUF ; Restore ACC value. RETI ; Exit interrupt vector Version 1.0 SONiX TECHNOLOGY CO., LTD Page 90...

  • Page 91: Serial Input/Output Transceiver (Sio)

    TRANSCEIVER (SIO) OVERVIEW The SN8P1829 provides an 8-bit SIO interface circuit with clock rate selection. The SIOM register can control SIO operating function, such as: transmit/receive, clock rate, transfer edge and starting this circuit. This SIO circuit TX or RX 8-bit data automatically by setting SENB and START bits in SIOM register. The SIOB is an 8-bit buffer, which is designed to store transfer data.
  • Page 92 SIOB 8 Bit Buffer SIOB 8 Bit Buffer SIOB 8 Bit Buffer SIOB 8 Bit Buffer SIO Clock SIO Clock PROCESS 1 PROCESS 1 PROCESS 2 PROCESS 2 Figure 10-2. SIO Data Transfer Diagram Version 1.0 SONiX TECHNOLOGY CO., LTD Page 92...

  • Page 93: Siom Mode Register

    Note 1: If SCKMD=1 for external clock, the SIO is in SLAVE mode. If SCKMD=0 for internal clock, the SIO is in MASTER mode. Note 2: Don’t set SENB and START bits in the same time. That makes the SIO function error. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 93...

  • Page 94: Siob Data Buffer

    Example: Setup the SIO clock to be 5KHz. F = 3.58MHz. SIO rate = F SIOR = 256 – (1/(5KHz) * 3.58MHz/4) = 256 – (0.0002*895000) = 256 – 179 = 77 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 94...

  • Page 95: Sio Master Operating Description

    ; Wait the end of SIO operation. CHK_END B0MOV A,SIOB ; Save SIOB data into RXDATA buffer. RXDATA,A TX/RX data Figure 10-4. The Rising Edge Timing Diagram of Master Transmit and Receive Operation Version 1.0 SONiX TECHNOLOGY CO., LTD Page 95...
  • Page 96 ; Wait the end of SIO operation. CHK_END B0MOV A,SIOB ; Save SIOB data into RXDATA buffer. RXDATA,A TX/RX data Figure 10-5. The Falling Edge Timing Diagram of Master Transmit and Receive Operation Version 1.0 SONiX TECHNOLOGY CO., LTD Page 96...
  • Page 97 ; Wait the end of SIO operation. CHK_END B0MOV A,SIOB ; Save SIOB data into RXDATA buffer. RXDATA,A RX data Normal I/O Application Figure 10-6. The Rising Edge Timing Diagram of Master Receiving Operation Version 1.0 SONiX TECHNOLOGY CO., LTD Page 97...
  • Page 98 ; Wait the end of SIO operation. CHK_END B0MOV A,SIOB ; Save SIOB data into RXDATA buffer. RXDATA,A RX data Normal I/O Application Figure 10-7. The Falling Edge Timing Diagram of Master Receiving Operation Version 1.0 SONiX TECHNOLOGY CO., LTD Page 98...

  • Page 99: Sio Slave Operating Description

    8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver SIO SLAVE OPERATING DESCRIPTION Under slave-receiver situation, the SCK has four phases as following. SCK1 SCK2 SCK3 SCK4 Figure 10-8. The Four Phases of SCK clock when SIO is Slave Operation. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 99...
  • Page 100 ; Wait the end of SIO operation. CHK_END B0MOV A,SIOB ; Save SIOB data into RXDATA buffer. RXDATA,A TX/RX data SCK1 TX/RX data SCK2 Figure 10-9. The Rising Edge Timing Diagram of Slave Transfer and Receiving Operation Version 1.0 SONiX TECHNOLOGY CO., LTD Page 100...
  • Page 101 ; Wait the end of SIO operation. CHK_END B0MOV A,SIOB ; Save SIOB data into RXDATA buffer. RXDATA,A TX/RX data SCK3 TX/RX data SCK4 Figure 10-10. The Falling Edge Timing Diagram of Slave Transfer and Receiving Operation Version 1.0 SONiX TECHNOLOGY CO., LTD Page 101...
  • Page 102 A,SIOB ; Save SIOB data into RXDATA buffer. RXDATA,A RX data SCK3 Normal I/O Application RX data SCK4 Normal I/O Application Figure 10-11. The Rising Edge Timing Diagram of Slave Receiving Operation Version 1.0 SONiX TECHNOLOGY CO., LTD Page 102...
  • Page 103 A,SIOB ; Save SIOB data into RXDATA buffer. RXDATA,A RX data SCK1 Normal I/O Application RX data SCK2 Normal I/O Application Figure 10-12. The Falling Edge Timing Diagram of Slave Receiving Operation Version 1.0 SONiX TECHNOLOGY CO., LTD Page 103...

  • Page 104: Sio Interrupt Operation Description

    ; Interrupt vector B0XCH A, ACCBUF PUSH B0BTS1 FSIOIRQ INT_EXIT B0MOV A,SIOB ; Save SIOB data into RXDATA buffer. RXDATA,A B0BCLR FSIOIRQ ; Clear SIO interrupt request flag. INT_EXIT: B0XCH A, ACCBUF Version 1.0 SONiX TECHNOLOGY CO., LTD Page 104...

  • Page 105: I/O Port

    8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver I/O PORT OVERVIEW The SN8P1829 provides up to four ports for users’ application, consisting of two input only ports (P0, P2), two I/O ports (P1, P5). The direction of I/O port is selected by P M register.

  • Page 106: I/O Port Function Table

    Bit 1 Bit 0 UR : The n expressed 0, 1, 2, 5. 7R ~ P 0R: Pull-up resistor control bit. 0 = Without pull up resistor 1 = With pull up resistor. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 106...

  • Page 107: I/O Port Mode

    ; Set all ports to be output mode. B0MOV P1M, A B0MOV P5M, A B0BCLR P1M.1 ; Set P1.1 to be input mode. B0BSET P1M.1 ; Set P1.1 to be output mode. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 107...

  • Page 108: The Port2 Discription

    ; Disable Pin 37 ~ 44 LCD driver. Step2: Now the PORT 2 general input function is enable. User can input data by PORT 2. B0MOV A, P2 ; Input Port 2 value to BUF. B0MOV BUF, A Version 1.0 SONiX TECHNOLOGY CO., LTD Page 108...

  • Page 109: I/O Port Data Register

    B0BCLR P1.3 ; Set P1.3 and P5.1 to be “0”. B0BCLR P5.1 Example: Port bit test. B0BTS1 P0.0 ; Bit test 1 for P0.0 B0BTS0 P1.1 ; Bit test 0 for P1.1 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 109...

  • Page 110: Lcd Driver

    LCD DRIVER There are 4 common pins and 32 segment pins in the SN8P1829. The LCD scan timing is 1/4 duty and 1/2,1/3 bias structure to yield 128 dots LCD driver. Of these pins, eight segment pins are shared with Port 2 and P2/SEG functions can be selected by programming LCDM1 register.
  • Page 111 In normal condition, the external bias resistor value is 100K ohm. Users can connect a resistor between VLCD and VDD to adjust the voltage level at VLCD pin or just connect VLCD to VDD directly. Figure 12-1. Example of circuit at each bias Version 1.0 SONiX TECHNOLOGY CO., LTD Page 111...

  • Page 112: Lcd Timing

    Note: The clock source of LCD driver is external low clock. LCD Clock 1 frame 1 frame VLCD COM0 V3 = V2 COM1 COM2 COM3 VLCD SEG0 Figure 12-2. LCD Drive Waveform, 1/4 duty, 1/2 bias Version 1.0 SONiX TECHNOLOGY CO., LTD Page 112...
  • Page 113 8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver LCD Clock 1 frame 1 frame VLCD COM0 COM1 COM2 COM3 VLCD SEG0 Figure 12-3. LCD Drive Waveform, 1/4 duty, 1/3 bias Version 1.0 SONiX TECHNOLOGY CO., LTD Page 113...

  • Page 114: Lcd Ram Location

    Enable the segment pin shared with PORT2. B0BCLR FP2SEG ; Enable SEG24~SEG31 Now all LCD pins are enabled. Set the LCD control bit (LCDENB) and program LCD RAM to display LCD panel. B0BSET FLCDENB ; LCD driver. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 114...

  • Page 115: 3-Channel Adc With Battery Monitor

    MONITOR OVERVIEW This analog to digital converter of SN8P1829 has three external input and one internal battery monitor channel. The resolution of ADC is up to 4096-step to transfer analog signal into 12-bits digital data. The sequence of ADC operation is to select input source (AIN0 ~ AIN3, AIN3 for battery monitor) at first, then set GCHS and ADS bit to “1”...

  • Page 116: Adm Register

    ADCKS1 ADCKS0 ADC Clock Source Note Fcpu/4 Both validate in Normal mode and Slow mode Fcpu/2 Both validate in Normal mode and Slow mode Fhosc Only validate in Normal mode Fhosc/2 Only validate in Normal mode Version 1.0 SONiX TECHNOLOGY CO., LTD Page 116...

  • Page 117: Adb Registers

    ADC converter routine. Then delete the LSB of ADC data and get the new resolution result. The table is as following. Resolution ADB11 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADB3 ADB2 ADB1 ADB0 8-bit 9-bit 10-bit 11-bit 12-bit O = Selected, x = Delete Version 1.0 SONiX TECHNOLOGY CO., LTD Page 117...

  • Page 118: Adc Converting Time

    FP4CON1 ;Pass AIN1 signal into ADC A,#91H B0MOV ADM,A ; To enable ADC and set AIN1 input B0BSET FADS ; To start conversion QEXADC: B0BCLR FGCHS ; To release AINx input channel Version 1.0 SONiX TECHNOLOGY CO., LTD Page 118...

  • Page 119: Charge-Pump, Pgia And Opa

    Charge-Pump, PGIA and OPA OVERVIEW The SN8P1829 has a built-in Voltage Charge-Pump/Regulator (CPR) to support a stable voltage 3.8V from pin AVDDR with maximum 5mA current driving capacity. This CPR provides stable voltage for internal circuits (PGIA, ADC and OPA) and external sensor (e.g. blood pressure sensor, thermistor, etc). The SN8P1829 also integrated 12-bit Analog-to-Digital Converters (ADC) up to 2048-step resolution.

  • Page 120: Voltage Charge-Pump Regulator (Cpr)

    VOLTAGE CHARGE-PUMP REGULATOR (CPR) SN8P1829 is built in a CPR, which can provide a stable 3.8V (pin AVDDR) with maximum 5mA current driving capacity. Register CPM can enable or disable CPR and controls CPR working mode, another register CPCKS sets CPR working clock to 100KHz.
  • Page 121 Note 2: For normally application, set CP as Auto mode (CPAUTO = 1) is strongly recommended. Note 3: If VDD is higher than 5.0V, don’t set Charge-Pump as Always ON mode. Note 4: The recommend operating voltage of PGIA, OPA and ADC are 3.8V Version 1.0 SONiX TECHNOLOGY CO., LTD Page 121...
  • Page 122 ; Set CPCKS = 236 for CP working clock = 100K @ 4M X’tal @CP_Enable: B0BSET FCPRENB ; Enable Charge-Pump / Regulator function @Delay_10ms: CALL @Wait_10ms ; Delay 10ms for Charge-Pump Stabilize … … Version 1.0 SONiX TECHNOLOGY CO., LTD Page 122...

  • Page 123: Programmable Gain Instrumentation Amplifier

    PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER (PGIA) SN8P1829 includes a low noise chopper-stabilized programmable gain instrumentation amplifier (PGIA) with selectable gains stage one of16x, 32x, 64x, 128x and gains stage two of 1.3x ~ 2.5x by register PGIAM. PGIAM- PGIA Mode Register...
  • Page 124 ;Set PGIACKS = 216 for PGIA working clock = 12.5K @ 4M X’tal @PGIA_Enable B0BSET FPGIAENB ; Enable PGIA function Note 1: Enable Charge-Pump/Regulator before PGIA working Note 2: Please set PGIA relative registers first, then enable PGIA function bit. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 124...

  • Page 125: Opa - Operational Amplifier

    8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver OPA – OPERATIONAL AMPLIFIER SN8P1829 provide two built-in operational amplifiers (OPA) for low pass filer or constant current source circuit. OPM- OPA Mode Register 09BH...

  • Page 126: Application Circuit

    LCD PANEL AIN1 AOUT VDD3A AIN2 AvrefH VDD3A AVREFH PGIABIAS PGIAIN+ PGIAIN- Gain2 Gain1 Sensor VDD3A SEG22 SEG23 PGIAOUT VDD1 VDD3A OP1IN+ SEG24 OP1IN- OP1OUT OP2IN+ OP2IN- OP2OUT VDD3A VBAT 10uF 32.768K Version 1.0 SONiX TECHNOLOGY CO., LTD Page 126...

  • Page 127: Instruction Set Table

    To push working registers (080H~087H) into buffers √ √ √ To pop working registers (080H~087H) from buffers No operation Table 16-1. Instruction Set Table of SN8P1829 Note: Any instruction that read/write from 0SCM, will add an extra cycle. Version 1.0 SONiX TECHNOLOGY CO., LTD Page 127...

  • Page 128: Electrical Characteristic

    (Stop High Clock) Vdd= 3V 32768Hz Vdd= 5V Idd4 Sleep mode Vdd= 3V Green Mode Vdd= 5V 32768Hz Idd5 (Stop High Clock) Vdd= 3V 32768Hz LVD detect level Internal POR detect level Version 1.0 SONiX TECHNOLOGY CO., LTD Page 128...
  • Page 129 Current driving capacity DRME Current sink capacity SINK Avdd-0.2 OPA output voltage range AVDDR = 3.8V O_OPA Charge pump regulator Supply voltage Normal mode Regulator output voltage Regulator output current capacity Quiescent current µA Version 1.0 SONiX TECHNOLOGY CO., LTD Page 129...

  • Page 130: Package Information

    SN8P1829 8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver PACKAGE INFORMATION LQFP80 Version 1.0 SONiX TECHNOLOGY CO., LTD Page 130...
  • Page 131 SONIX product could create a situation where personal injury or death may occur.

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