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SN8P2604
USER'S MANUAL
Version 1.1
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
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8-Bit Micro-Controller
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SN8P2604
Version 1.1
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Related Manuals for SONIX SN8P2604
Summary of Contents for SONIX SN8P2604
- Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.
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Page 2: Amendent History
7. Remove ORG4~7 limitation. VER 1.1 Jan. 2005 1. Re-arrange partial edition layout. 2. Strongly recommend using SN8ICE-2K ICE to emulate SN8P2604. SN8IDE V1.99S or later No More support SN8P2000 series emulation. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 2... -
Page 3: Table Of Contents
Y, Z REGISTERS......................... 33 2.1.4.8 R REGISTERS ........................34 ADDRESSING MODE ........................35 2.2.1 IMMEDIATE ADDRESSING MODE..................35 2.2.2 DIRECTLY ADDRESSING MODE ..................35 2.2.3 INDIRECTLY ADDRESSING MODE ..................35 STACK OPERATION ........................36 Version 1.1 SONiX TECHNOLOGY CO., LTD Page 3... - Page 4 SYSTEM CLOCK MEASUREMENT ..................50 SYSTEM OPERATION MODE ....................51 OVERVIEW............................. 51 SYSTEM MODE SWITCHING ...................... 52 WAKEUP ............................54 5.3.1 OVERVIEW ..........................54 5.3.2 WAKEUP TIME........................54 5.3.3 P1W WAKEUP CONTROL REGISTER ................... 55 Version 1.1 SONiX TECHNOLOGY CO., LTD Page 4...
- Page 5 TC1M MODE REGISTER ......................78 8.3.3 TC1C COUNTING REGISTER ....................79 8.3.4 TC1R AUTO-LOAD REGISTER ....................80 8.3.5 TC1 CLOCK FREQUENCY OUTPUT (BUZZER) ..............81 8.3.6 TC1 TIMER OPERATION SEQUENCE .................. 82 Version 1.1 SONiX TECHNOLOGY CO., LTD Page 5...
- Page 6 S8KD-2 ICE ENULATION ......................96 11.5.1 ICE_MODE ..........................96 11.5.2 INSTRUCTION CYCLE......................97 11.5.3 SYSTEM CLOCK........................99 11.5.4 WATCHDOG TIMER ......................100 11.5.5 P0 EMULATION ........................101 11.5.5.1 @P00_MODE, @P01_MODE..................101 11.5.5.2 @P00_OUT, @P01_OUT ....................102 Version 1.1 SONiX TECHNOLOGY CO., LTD Page 6...
- Page 7 The pin assignment of Easy Writer transition board socket: ..........106 12.1.2 The pin assignment of Writer V3.0 and V2.5 transition board socket: ........106 12.1.3 SN8P2604 Programming Pin Mapping: ................107 PACKAGE INFORMATION ..................... 108 13.1 SK-DIP 28 PIN..........................108 13.2...
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Page 8: Product Overview
SOP 20 pins SSOP 20 pins Features Selection Table Timer Green Wakeup CHIP ROM RAM Stack Package Mode Buzzer Pin No. SN8P1604A 4K*16 128 SK-DIP28/SOP28 SN8P2604 4K*16 128 SK-DIP28/SOP28/SSOP28 SN8P26042 4K*16 128 P-DIP20/SOP20/SSOP20 Version 1.1 SONiX TECHNOLOGY CO., LTD Page 8... - Page 9 SN8P2604 8-Bit Micro-Controller Migration SN8P1604A to SN8P2604 Item SN8P2604 SN8P1604A Not available Available PUSH/POP Available Not available B0MOV M, I I can’t be 0E6h or 0E7h The address of M can’t be B0XCH A, M 80h~FFh Valid instruction in ROM address 8...
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Page 10: System Block Diagram
PWM & BUZZER SYSTEM REGISTER SYSTEM REGISTER INTERRUPT INTERRUPT TIMER & COUNTER TIMER & COUNTER CONTROL CONTROL PORT 0 PORT 0 PORT 5 PORT 5 PORT 1 PORT 1 PORT 2 PORT 2 Version 1.1 SONiX TECHNOLOGY CO., LTD Page 10... -
Page 11: Pin Assignment
20 P5.0 P5.3/BZ1/PWM 19 P0.0/INT0 P1.0 18 VSS P1.1 17 VDD P1.2 16 P0.1 P1.3 15 RST/VPP/P0.2 P1.4 14 XIN P1.5 13 XOUT/Fcpu P1.6 12 P2.7 P1.7 10 11 P2.0 SN8P26042P SN8P26042S SN8P26042X Version 1.1 SONiX TECHNOLOGY CO., LTD Page 11... -
Page 12: Pin Descriptions
Port 5 bi-direction pin. Schmitt trigger structure as input mode. P5.0~P5.2, P5.4 Built-in pull-up resisters. Port 5.3 bi-direction pin. Schmitt trigger structure as input mode. P5.3/BZ1/PWM1 Built-in pull-up resisters. TC1 ÷ 2 signal output pin for buzzer or PWM1 output pin. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 12... -
Page 13: Pin Circuit Diagrams
Input Bus Output Output Bus Latch Port 1.0, P1.1 structure: Pull-Up PnM, PnUR Input Bus Output Output Bus Latch Open-Drain P1OC Port 0.2 structure: Ext. Reset Code Option Int. Bus Int. Rst Version 1.1 SONiX TECHNOLOGY CO., LTD Page 13... -
Page 14: Central Processor Unit (Cpu)
0004H 0005H General purpose area 0006H 0007H Interrupt vector 0008H User interrupt vector 0009H User program 000FH 0010H 0011H General purpose area 0FFBH End of user program 0FFCH 0FFDH Reserved 0FFEH 0FFFH Version 1.1 SONiX TECHNOLOGY CO., LTD Page 14... -
Page 15: Reset Vector (0000H)
Example: Defining Reset Vector ; 0000H START ; Jump to user program address. … START: ; 0010H, The head of user program. … ; User program … ENDP ; End of program Version 1.1 SONiX TECHNOLOGY CO., LTD Page 15... -
Page 16: Interrupt Vector (0008H)
RETI ; End of interrupt service routine … START: ; The head of user program. … ; User program … START ; End of user program … ENDP ; End of program Version 1.1 SONiX TECHNOLOGY CO., LTD Page 16... - Page 17 ENDP ; End of program. Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
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Page 18: Look-Up Table Description
Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Example: INC_YZ macro. INC_YZ MACRO INCMS ; Z+1 ; Not overflow INCMS ; Y+1 ; Not overflow ENDM Version 1.1 SONiX TECHNOLOGY CO., LTD Page 18... - Page 19 0x0100 ; Set TABLE1 start address is 0x0100 to avoid “B0MOV M, I” instruction doesn’t support “I=0xE6” and “I=0xE7”. TABLE1: 0035H ; To define a word (16 bits) data. 5105H 2012H … Version 1.1 SONiX TECHNOLOGY CO., LTD Page 19...
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Page 20: Jump Table Description
; ACC = 3, jump to A3POINT SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size. - Page 21 SN8P2604 8-Bit Micro-Controller Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”. B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A ; The number of the jump table listing is five. A0POINT ; ACC = 0, jump to A0POINT A1POINT ;...
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Page 22: Checksum Calculation
; If Not jump to checksum calculate CHECKSUM_END ; If Yes checksum calculated is done. Y_ADD_1: INCMS ; Increase Y ; Jump to checksum calculate CHECKSUM_END: … … END_USER_CODE: ; Label of program end Version 1.1 SONiX TECHNOLOGY CO., LTD Page 22... -
Page 23: Code Option Table
If users define watchdog as “Always_On”, assembler will Enable “Watch_Dog” automatically. Fcpu code option is only available for High Clock. Fcpu of slow mode is Fosc/4 (the Fosc is internal low clock). Version 1.1 SONiX TECHNOLOGY CO., LTD Page 23... -
Page 24: Data Memory (Ram)
General purpose area “ “ “ 07Fh BANK 0 080h 080h~0FFh of Bank 0 store system registers (128 bytes). “ “ System register “ “ “ End of bank 0 area 0FFh Version 1.1 SONiX TECHNOLOGY CO., LTD Page 24... -
Page 25: System Register
WDTR = Watchdog timer clear register. STKP = Stack pointer buffer. STK0~STK7 = Stack 0 ~ stack 7 buffer. @YZ = RAM YZ indirect addressing index pointer. @HL = RAM HL indirect addressing index pointer. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 25... -
Page 26: Bit Definition Of System Register
3. One-bit name had been declared in SN8ASM assembler with “F” prefix code. 4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers. 5. For detail description, please refer to the “System Register Quick Reference Table” Version 1.1 SONiX TECHNOLOGY CO., LTD Page 26... -
Page 27: Accumulator
“PUSH”, “POP” save and load ACC, PFLAG data into buffers. Example: Protect ACC and working registers. INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector Version 1.1 SONiX TECHNOLOGY CO., LTD Page 27... -
Page 28: Program Flag
0 = Arithmetic without carry from low nibble, subtraction with borrow from high nibble. Bit 0 Z: Zero flag 1 = ACC is zero after executing a instruction. 0 = ACC is not zero after executing a instruction. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 28... -
Page 29: Program Counter
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. CMPRS A, #12H ; To skip, if ACC = 12H. C0STEP ; Else jump to C0STEP. … … C0STEP: Version 1.1 SONiX TECHNOLOGY CO., LTD Page 29... - Page 30 DECS BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: DECMS instruction: DECMS BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: Version 1.1 SONiX TECHNOLOGY CO., LTD Page 30...
- Page 31 ; If ACC = 0, jump to A0POINT A1POINT ; ACC = 1, jump to A1POINT A2POINT ; ACC = 2, jump to A2POINT A3POINT ; ACC = 3, jump to A3POINT … … Version 1.1 SONiX TECHNOLOGY CO., LTD Page 31...
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Page 32: H, L Registers
; Clear @HL to be zero DECMS ; L – 1, if L = 0, finish the routine CLR_HL_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … … Version 1.1 SONiX TECHNOLOGY CO., LTD Page 32... -
Page 33: Y, Z Registers
; Clear @YZ to be zero DECMS ; Z – 1, if Z= 0, finish the routine CLR_YZ_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … Version 1.1 SONiX TECHNOLOGY CO., LTD Page 33... -
Page 34: R Registers
Bit 3 Bit 2 Bit 1 Bit 0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Read/Write After reset Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 34... -
Page 35: Addressing Mode
; To clear Y register to access RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 35... -
Page 36: Stack Operation
STKP = 5 STK5H STK5L STKP STKP STKP = 4 STK4H STK4L STKP = 3 STK3H STK3L STKP = 2 STK2H STK2L STKP = 1 STK1H STK1L STKP = 0 STK0H STK0L Version 1.1 SONiX TECHNOLOGY CO., LTD Page 36... -
Page 37: Stack Registers
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKnL SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0 Read/Write After reset STKn = STKnH , STKnL (n = 7 ~ 0) Version 1.1 SONiX TECHNOLOGY CO., LTD Page 37... -
Page 38: Stack Operation Example
STKP Register Stack Buffer Stack Level Description STKPB2 STKPB1 STKPB0 High Byte Low Byte STK7H STK7L STK6H STK6L STK5H STK5L STK4H STK4L STK3H STK3L STK2H STK2L STK1H STK1L STK0H STK0L Free Free Version 1.1 SONiX TECHNOLOGY CO., LTD Page 38... -
Page 39: Reset
NT0, NPD: Reset status flag. Condition Description Watchdog reset Watchdog timer overflow. Reserved Power on reset and LVD reset. Power voltage is lower than LVD detecting level. External reset External reset pin detect low level status. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 39... - Page 40 High Detect Low Detect Watchdog Overflow Watchdog Normal Run Watchdog Reset Watchdog Stop System Normal Run System Status System Stop Power On External Watchdog Delay Time Reset Delay Reset Delay Time Time Version 1.1 SONiX TECHNOLOGY CO., LTD Page 40...
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Page 41: Power On Reset
Oscillator warm up: Oscillator operation is successfully and supply to system clock. Program executing: Power on sequence is finished and program executes from ORG 0. Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 41... -
Page 42: External Reset
Program executing: Power on sequence is finished and program executes from ORG 0. 3.4.1 EXTERNAL RESET CIRCUIT The external reset circuit is a simple RC circuit as the following diagram. 0.1uF 0.1uF Simply RC Reset Circuit Diode Reset Circuit for Brownout Reset Version 1.1 SONiX TECHNOLOGY CO., LTD Page 42... -
Page 43: Low Voltage Detector (Lvd)
LVD Detect Voltage Power Power Drops to < LVD Detect Voltage and System Reset. System Normal Run System Status System Stop Power On Delay Time Brown Out Reset Diagram Version 1.1 SONiX TECHNOLOGY CO., LTD Page 43... -
Page 44: System Clock
Fcpu = Flosc/4. SONIX provides a “Noise Filter” controlled by code option. In high noisy situation, the noise filter can isolate noise outside and protect system works well. The minimum Fcpu of high clock is limited at Fhosc/4 when noise filter enable. -
Page 45: Oscm Register
Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal low-speed oscillator will be stopped. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Version 1.1 SONiX TECHNOLOGY CO., LTD Page 45... -
Page 46: System High Clock
High_Clk code option. The start up time of crystal/ceramic and RC type oscillator is different. RC type oscillator’s start-up time is very short, but the crystal’s is longer. The oscillator start-up time decides reset time length. 4MHz Crystal 32768Hz Crystal 4MHz Ceramic Version 1.1 SONiX TECHNOLOGY CO., LTD Page 46... -
Page 47: Crystal/Ceramic
“R” value is to change frequency. 50P~100P is good value for “C”. XOUT pin is general purpose I/O pin. Note: Connect the R and C as near as possible to the VDD pin of micro-controller. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 47... -
Page 48: External Clock Signal
XIN pin. XOUT pin is general purpose I/O pin. External Clock Input XOUT Note: The GND of external oscillator circuit must be as near as possible to VSS pin of micro-controller. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 48... -
Page 49: System Low Clock
; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1 (32K, watchdog disable) bits of OSCM register. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 49... -
Page 50: System Clock Measurement
; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P0.0 ; Measure the Fcpu frequency by oscilloscope. Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC frequency. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 50... -
Page 51: System Operation Mode
All active All active All active All inactive P0, P1, T0 Wakeup source P0, P1, Reset Reset EHOSC: External high clock ILRC: Internal low clock (16K RC oscillator at 3V, 32K at 5V) Version 1.1 SONiX TECHNOLOGY CO., LTD Page 51... -
Page 52: System Mode Switching
; Set CPUM1 = 1. Note: If T0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can wakeup the system backs to the previous operation mode. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 52... - Page 53 Note: During the green mode with T0 wake-up function, the wakeup pins, reset pin and T0 can wakeup the system back to the last mode. T0 wake-up period is controlled by program and T0ENB must be set. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 53...
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Page 54: Wakeup
The wakeup time is as the following. The wakeup time = 1/Fosc * 2048 = 0.512 ms (Fosc = 4MHz) The total wakeup time = 0.512ms + oscillator start-up time Version 1.1 SONiX TECHNOLOGY CO., LTD Page 54... -
Page 55: P1W Wakeup Control Register
Bit 0 P17W P16W P15W P14W P13W P12W P11W P10W Read/Write After reset Bit[7:0] P10W~P17W: Port 1 wakeup function control bits. 0 = Disable P1n wakeup function. 1 = Enable P1n wakeup function. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 55... -
Page 56: Interrupt
INT1 Trigger Interrupt Vector Address (0008H) 4-Bit Enable T0IRQ T0 Time Out Global Interrupt Request Signal Latchs Gating TC1IRQ TC1 Time Out Note: The GIE bit must enable during all interrupt operation. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 56... -
Page 57: Inten Interrupt Enable Register
0 = Disable T0 interrupt function. 1 = Enable T0 interrupt function. Bit 6 TC1IEN: TC1 timer interrupt control bit. 0 = Disable TC1 interrupt function. 1 = Enable TC1 interrupt function. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 57... -
Page 58: Intrq Interrupt Request Register
T0IRQ: T0 timer interrupt request flag. 0 = None T0 interrupt request. 1 = T0 interrupt request. Bit 6 TC1IRQ: TC1 timer interrupt request flag. 0 = None TC1 interrupt request. 1 = TC1 interrupt request. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 58... -
Page 59: Gie Global Interrupt Operation
0 = Disable global interrupt. 1 = Enable global interrupt. Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE Note: The GIE bit must enable during all interrupt operation. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 59... -
Page 60: Push, Pop Routine
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine executed. START INT_SERVICE START: … INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector … ENDP Version 1.1 SONiX TECHNOLOGY CO., LTD Page 60... -
Page 61: Int0 (P0.0) Interrupt Operation
; P00IRQ = 0, exit interrupt vector B0BCLR FP00IRQ ; Reset P00IRQ … ; INT0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.1 SONiX TECHNOLOGY CO., LTD Page 61... -
Page 62: Int1 (P0.1) Interrupt Operation
; P01IRQ = 0, exit interrupt vector B0BCLR FP01IRQ ; Reset P01IRQ … ; INT1 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.1 SONiX TECHNOLOGY CO., LTD Page 62... -
Page 63: T0 Interrupt Operation
A, #74H B0MOV T0C, A ; Reset T0C. … ; T0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.1 SONiX TECHNOLOGY CO., LTD Page 63... -
Page 64: Tc1 Interrupt Operation
A, #74H B0MOV TC1C, A ; Reset TC1C. … ; TC1 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.1 SONiX TECHNOLOGY CO., LTD Page 64... -
Page 65: Multi-Interrupt Operation
; Jump to exit of IRQ B0BTS0 FTC1IRQ ; Check TC1IRQ INTTC1 ; Jump to TC1 interrupt service routine INT_EXIT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.1 SONiX TECHNOLOGY CO., LTD Page 65... -
Page 66: I/O Port
; Set all ports to be output mode. B0MOV P0M, A B0MOV P1M, A B0MOV P2M, A B0MOV P5M, A B0BCLR P1M.2 ; Set P1.2 to be input mode. B0BSET P1M.2 ; Set P1.2 to be output mode. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 66... -
Page 67: I/O Pull Up Register
Note: P0.2 is input only pin and without pull-up resister. The P0UR.2 keeps “1”. Example: I/O Pull up Register A, #0FFH ; Enable Port0, 1, 2, 5 Pull-up register, B0MOV P0UR, A B0MOV P1UR, A B0MOV P2UR, A B0MOV P5UR, A Version 1.1 SONiX TECHNOLOGY CO., LTD Page 67... -
Page 68: I/O Open-Drain Register
Example: Disable P1.0 to open-drain mode and output low. A, #0 ; Disable P1.0 open-drain function. B0MOV P1OC, A Note: After disable P1.0 open-drain function, P1.0 mode returns to last I/O mode. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 68... -
Page 69: I/O Port Data Register
Example: Write one bit data to output port. B0BSET P1.3 ; Set P1.3 and P5.5 to be “1”. B0BSET P5.5 B0BCLR P1.3 ; Set P1.3 and P5.5 to be “0”. B0BCLR P5.5 Version 1.1 SONiX TECHNOLOGY CO., LTD Page 69... -
Page 70: Timers
Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer. 0CCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTR WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0 Read/Write After reset Version 1.1 SONiX TECHNOLOGY CO., LTD Page 70... - Page 71 … … CALL SUB1 CALL SUB2 … … MAIN Example: Clear watchdog timer by @RST_WDT macro. Main: @RST_WDT ; Clear the watchdog timer. … … CALL SUB1 CALL SUB2 … … MAIN Version 1.1 SONiX TECHNOLOGY CO., LTD Page 71...
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Page 72: Timer 0 (T0)
Green mode wakeup function: T0 can be green mode wake-up time as T0ENB = 1. System will be wake-up by T0 time out. T0 Rate (Fcpu/2~Fcpu/256) T0ENB Internal Data Bus Load Fcpu T0C 8-Bit Binary Up Counting Counter T0 Time Out CPUM0,1 Version 1.1 SONiX TECHNOLOGY CO., LTD Page 72... -
Page 73: T0M Mode Register
T0RATE[2:0]: T0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. … 110 = fcpu/4. 111 = fcpu/2. Bit 7 T0ENB: T0 counter control bit. 0 = Disable T0 timer. 1 = Enable T0 timer. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 73... -
Page 74: T0C Counting Register
Fcpu/4 1.024 ms 4 us 125 ms 488.281 us Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us Note: T0C doesn’t support read and modify write instructions as “B0ADD M,A . INCMS…”. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 74... -
Page 75: T0 Timer Operation Sequence
Set T0 interrupt interval time. A,#7FH B0MOV T0C,A ; Set T0C value. Set T0 timer function mode. B0BSET FT0IEN ; Enable T0 interrupt function. Enable T0 timer. B0BSET FT0ENB ; Enable T0 timer. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 75... -
Page 76: T0 Timer Notice
Note: Disable T0 interrupt function first, and load new T0C value into T0C buffer. This way can avoid unexpected T0 interrupt occurring. Note: T0C doesn’t support read and modify write instructions as “B0ADD M,A . INCMS…”. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 76... -
Page 77: Timer/Counter 1 (Tc1)
Auto. Reload TC1 / 2 P5.3 TC1R Reload Data Buffer PWM1OUT TC1 Rate Compare (Fcpu/2~Fcpu/256) TC1CKS TC1ENB Load Fcpu TC1C 8-Bit Binary Up TC1 Time Out Counting Counter INT1 (Schmitter Trigger) CPUM0,1 Version 1.1 SONiX TECHNOLOGY CO., LTD Page 77... -
Page 78: Tc1M Mode Register
0 = Disable TC1 timer. 1 = Enable TC1 timer. Note: When TC1CKS=1, TC1 became an external event counter and TC1RATE is useless. No more P0.1 interrupt request will be raised. (P0.1IRQ will be always 0). Version 1.1 SONiX TECHNOLOGY CO., LTD Page 78... -
Page 79: Tc1C Counting Register
16 us 500 ms 1953.125 us Fcpu/8 2.048 ms 8 us 250 ms 976.563 us Fcpu/4 1.024 ms 4 us 125 ms 488.281 us Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us Version 1.1 SONiX TECHNOLOGY CO., LTD Page 79... -
Page 80: Tc1R Auto-Load Register
TC1R initial value = N - (TC1 interrupt interval time * input clock) = 256 - (10ms * 4MHz / 4 / 64) = 256 - (10 * 4 * 10 / 4 / 64) = 100 = 64H Version 1.1 SONiX TECHNOLOGY CO., LTD Page 80... -
Page 81: Tc1 Clock Frequency Output (Buzzer)
; Enable TC1 output to P5.3 and disable P5.3 I/O function B0BSET FALOAD1 ; Enable TC1 auto-reload function B0BSET FTC1ENB ; Enable TC1 timer Note: Buzzer output is enable, and “PWM1OUT” must be “0”. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 81... -
Page 82: Tc1 Timer Operation Sequence
; ALOAD1, TC1OUT = 01, PWM cycle boundary is 0~63. B0BSET FTC1OUT B0BSET FALOAD1 ; ALOAD1, TC1OUT = 10, PWM cycle boundary is 0~31. B0BCLR FTC1OUT B0BSET FALOAD1 ; ALOAD1, TC1OUT = 11, PWM cycle boundary is 0~15. B0BSET FTC1OUT Version 1.1 SONiX TECHNOLOGY CO., LTD Page 82... - Page 83 Set TC1 timer function mode. B0BSET FTC1IEN ; Enable TC1 interrupt function. B0BSET FTC1OUT ; Enable TC1OUT (Buzzer) function. B0BSET FPWM1OUT ; Enable PWM function. Enable TC1 timer. B0BSET FTC1ENB ; Enable TC1 timer. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 83...
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Page 84: Tc1 Timer Notice
; Clear TC1IRQ flag. B0BSET FTC1IEN ; Enable TC1 interrupt function. … … Note: Disable TC1 interrupt function first, and load new TC1C value into TC1C buffer. This way can avoid unexpected TC1 interrupt occurring. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 84... -
Page 85: Pwm1 Mode
125K Overflow per 16 count The Output duty of PWM is with different TC1R. Duty range is from 0/256~255/256. …… …… …… …… TC1 Clock TC1R=00H High TC1R=01H High TC1R=80H High TC1R=FFH Version 1.1 SONiX TECHNOLOGY CO., LTD Page 85... -
Page 86: Tc1Irq And Pwm Duty
PWM duty. TC1 Overflow, TC1IRQ = 1 0xFF TC1C Value 0x00 PWM1 Output (Duty Range 0~255) PWM1 Output (Duty Range 0~63) PWM1 Output (Duty Range 0~31) PWM1 Output (Duty Range 0~15) Version 1.1 SONiX TECHNOLOGY CO., LTD Page 86... -
Page 87: Pwm Program Example
TC1R, A INCMS BUF0 ; Get the new TC1R value from the BUF0 buffer defined by ; programming. B0MOV A, BUF0 B0MOV TC1R, A Note: The PWM can work with interrupt request. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 87... -
Page 88: Pwm1 Duty Changing Notice
Above diagram is shown the waveform with fixed TC1R. In every TC1C overflow PWM output “High, when TC1C≧ TC1R PWM output ”Low”. Note: Setting PWM duty in program processing must be at the new cycle start. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 88... - Page 89 … B0BTS1 FTC1IRQ INT_SER90 B0MOV A, TC1RBUF ; When TC1 Interrupt occurs, update TC1R. B0MOV TC1R, A … … INT_SER90: … ; Pop routine to load ACC and PFLAG from buffers. RETI Version 1.1 SONiX TECHNOLOGY CO., LTD Page 89...
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Page 90: Instruction Table
2. If branch condition is true then “S = 0”, otherwise “S = 1”. 3. “I” of “B0MOV M,I” doesn’t support “E6h” and “E7h”. 4. “M” of “B0XCH” doesn’t support 0x80~0xFF system registers. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 90... -
Page 91: Electrical Characteristic
Fcpu = Fosc/4, Low Vdd= 3V, 32768Hz Power Disable) Vdd=5V, ILRC 32Khz Vdd=3V, ILRC 16Khz Internal Oscillator Freq. Filrc Internal Low RC (ILRC) Vdd= 3V LVD detect level Low voltage detect level Version 1.1 SONiX TECHNOLOGY CO., LTD Page 91... -
Page 92: Application Notice
MP-Easy Writer V1.0: Stand-alone operation to support SN8P2604 mass production 11.1.3 SN8IDE SONiX 8-bit MCU integrated development environment include Assembler, ICE debugger and OTP writer software. For S8KD-2 ICE: SN8IDE_V1.99R. SN8IDE V1.99S or later No More support SN8P2000 series emulation. -
Page 93: Code Option
11.2.1 FCPU CODE OPTION SN8P2604 is a 1T (one clock per instruction cycle) system MCU. For different applications, users can select different instruction cycle clock (Fcpu) by Fcpu code option from Fosc/1 to Fosc/8. Compiler limits Fcpu range for different application automatically as following. -
Page 94: Interrupt Vector (Org 8)
; User program. … … START ; End of user program. … MY_IRQ: ;The head of interrupt service routine. … ; End of interrupt service routine. RETI … ENDP ; End of program. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 94... -
Page 95: Instruction
PFLAGBUF, A Correct case! B0MOV A, PFLAG B0MOV PFLAGBUF, A ; PFLAGBUF is user defining RAM, Example: Save ACC. ; Define ACCBUF to be ACC buffer. ACCBUF … … B0XCH A, ACCBUF … Version 1.1 SONiX TECHNOLOGY CO., LTD Page 95... -
Page 96: S8Kd-2 Ice Enulation
SN8IDE is SONIX 8-bit development software including Assembler/ICE Debugger/OTP Writer. S8KD-2 is SONIX 8-bit ICE EV chip. There are different specifications between SN8P2604 and EV Chip. SONIX provides macros to solve the difference and make emulation correct. SN8IDE_V1.99R_S8KD2 and later version support these macros. -
Page 97: Instruction Cycle
8-Bit Micro-Controller 11.5.2 INSTRUCTION CYCLE Instruction cycles of some instructions are different between SN8P2604 and EV chip. These differences makes ICE instruction timing isn’t consistent with SN8P2604. SN8IDE assembler provides some macros to solve instruction cycle difference as following. Users just only use built-in instruction macro to replace corresponding instruction. In “ICE_MODE EQU 1”... - Page 98 SN8P2604 8-Bit Micro-Controller Note: S8KD-2 ICE can’t emulate SN8P2604’s “PUSH, POP” instructions. Note: The instruction macros of above table are built in “SN8P2X_ICE.H”. The file must be included in user program. Example: Including SN8P2X_ICE.H in user program. CHIP SN8P2604 .DATA...
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Page 99: System Clock
SONIX 2 series 8-bit MCU has multi-system clock (Fosc/1~Fosc/8,Fosc/64,Fosc/8,), but ICE is fixed Fosc/4. In ICE emulation, user must be sure the Fcpu speeds of SN8P2604 and ICE are identical. Before emulation, change ICE crystal frequency to match with SN8P2604 system clock. -
Page 100: Watchdog Timer
SN8P2604 8-Bit Micro-Controller 11.5.4 WATCHDOG TIMER Watchdog timer clear routine of SN8P2604 is setting WDTR register 0x5A. S8KD-2 ICE is not. SN8IDE provides “@RST_WDT” macro to make watchdog timer function correctly. Example: Reset watchdog timer by setting WDTR as 0x5A. -
Page 101: P0 Emulation
SN8P2604 8-Bit Micro-Controller 11.5.5 P0 EMULATION SN8P2604’s P0.0 is bi-direction I/O, but ICE’s P0.0 is input only. PEDGE controls are different, too. SN8IDE provides macros to control P0.0 emulation. These macros are built in assembler software. 11.5.5.1 @P00_MODE, @P01_MODE Syntax: @P00_MODE Val: 0 = Set P0.0 input mode. -
Page 102: P00_Out, @P01_Out
Val: 0 = Set P0.1 output low. 1 = Set P0.1 output high. Example: Set P0.0 as output high. @P00_OUT Example: Set P0.0 as output low. @P00_OUT Note: Under P0.0/P0.1 output mode, the signals are output from P6.0/P6.1 of S8KD-2 ICE. Version 1.1 SONiX TECHNOLOGY CO., LTD Page 102... -
Page 103: Pedge
Bi-Direction Bi-Direction SONIX provides “@P00_EDGE” macro to emulate real chip PEDGE function in ICE. The ICE_MODE must be 1 for ICE Emulation. After ICE emulation, set ICE_MODE as 0 and compile again to get SN8 file for real chip. Syntax: @P00_EDGE Val: 1 = Rising edge. -
Page 104: Pwm Duty
Overflow per 16 count S8KD-2 ICE doesn’t support PWM duty setting function. SONIX provides PWM Duty setting macro. Users can use it to emulate PWM function and don’t affect other functions. The macro is built in assembler software. Users have to set ICE_MODE as ICE or real chip. -
Page 105: Other Macro
… @@.Macro_Start: @RST_WDT @@.Macro_End: TEST_CODE: … Note: Only S8ASM V1.99L or later version support user defined forward/backward jump directive! Note: Macro possible affects Accumulator and PFLAG result. Users have to check it! Version 1.1 SONiX TECHNOLOGY CO., LTD Page 105... -
Page 106: Otp Programming Pin
18 HLS Writer V2.5 JP1 Pin Assignment Writer V3.0 JP1 Pin Assignment Note: For supporting the body programming, SONIX writer V2.5 must update V3.0 firmware and modify circuit. Please contact SONIX agent about SONIX Writer V2.5 upgrade. Version 1.1 SONiX TECHNOLOGY CO., LTD... -
Page 107: Sn8P2604 Programming Pin Mapping
SN8P2604 8-Bit Micro-Controller 12.1.3 SN8P2604 Programming Pin Mapping: Programming Information of SN8P2600A Series Chip Name SN8P2604 SN8P26042 EZ Writer / Writer Writer V2.5 V3.0 OTP IC / JP3 Pin Assigment Connector Connector Number Name Number Name Number Number P5.0 P5.0 P1.0... -
Page 108: Package Information
1.400 35.306 35.306 35.560 0.310 7.874 0.283 0.288 0.293 7.188 7.315 7.442 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.330 0.350 0.370 8.382 8.890 9.398 θ° 0° 7° 15° 0° 7° 15° Version 1.1 SONiX TECHNOLOGY CO., LTD Page 108... -
Page 109: Sop 28 Pin
0.305 0.697 0.705 0.713 17.704 17.907 18.110 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.325 10.643 0.016 0.033 0.050 0.406 0.838 1.270 θ° 0° 4° 8° 0° 4° 8° Version 1.1 SONiX TECHNOLOGY CO., LTD Page 109... -
Page 110: Ssop 28 Pin
0.39 0.40 0.41 7.40 7.80 8.20 0.29 0.31 0.32 5.00 5.30 5.60 0.20 0.21 0.22 0.0259BSC 0.65BSC 0.63 0.90 1.03 0.02 0.04 0.04 0.09 0.00 θ° 0° 4° 8° 0° 4° 8° Version 1.1 SONiX TECHNOLOGY CO., LTD Page 110... -
Page 111: P-Dip 20 Pin
1.060 24.892 26.162 26.924 0.300 7.620 0.245 0.250 0.255 6.223 6.350 6.477 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.335 0.355 0.375 8.509 9.017 9.525 θ° 0° 7° 15° 0° 7° 15° Version 1.1 SONiX TECHNOLOGY CO., LTD Page 111... -
Page 112: Sop 20 Pin
0.305 0.496 0.502 0.508 12.598 12.751 12.903 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.325 10.643 0.016 0.033 0.050 0.406 0.838 1.270 θ° 0° 4° 8° 0° 4° 8° Version 1.1 SONiX TECHNOLOGY CO., LTD Page 112... -
Page 113: Ssop 20 Pin
3.800 3.900 4.000 0.025 0.635 0.010 0.017 0.020 0.250 0.420 0.500 0.016 0.025 0.050 0.400 0.635 1.270 0.039 0.041 0.043 1.000 1.050 1.100 0.059 1.500 0.004 0.100 θ° 0° 8° 0° 8° Version 1.1 SONiX TECHNOLOGY CO., LTD Page 113... - Page 114 SONIX product could create a situation where personal injury or death may occur.
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