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SN8P26L38
USER'S MANUAL
Version 1.5
SN8P26L38
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
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8-Bit Micro-Controller
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Version 1.5
SN8P26L38
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Table of Contents
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Summary of Contents for SONIX SN8P26L38
- Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.
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Page 2: Amendment History
The 1E6H, 1E7H of RAM address doesn’t support directly addressing mode to VER 1.3 Apr. 2013 access RAM but support indirectly addressing mode @HL/@YZ. Modify “SIO chapter” SCK frequency formula and description. VER 1.4 Aug. 2013 VER 1.5 Jan. 2019 Delete SSOP48 package. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 2... -
Page 3: Table Of Contents
2.4.1 OVERVIEW ............................. 36 2.4.2 STACK REGISTERS ........................37 2.4.3 STACK OPERATION EXAMPLE ....................38 2.5 CODE OPTION TABLE ........................39 2.5.1 RESET_PIN CODE OPTION ......................39 2.5.2 SECURITY CODE OPTION ......................39 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 3... - Page 4 5.3 SLOW MODE............................57 5.4 POWER DOWN MDOE ......................... 57 5.5 GREEN MODE............................58 5.6 OPERATING MODE CONTROL MACRO ..................58 5.7 WAKEUP ............................... 60 5.7.1 OVERVIEW ............................. 60 5.7.2 WAKEUP TIME ..........................60 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 4...
- Page 5 8.3.3 T1CH, T1CL COUNTING REGISTER .................... 90 8.3.4 T1 TIMER OPERATION SEQUENCE .................... 92 8.4 TIMER/COUNTER 0 (TC1) ........................93 8.4.1 OVERVIEW ............................. 93 8.4.2 TC1M MODE REGISTER ....................... 94 8.4.3 TC1C COUNTING REGISTER ....................... 95 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 5...
- Page 6 12.3 UART RECEIVER CONTROL REGISTER ..................123 12.4 UART TRANSMITTER CONTROL REGISTER ................123 12.5 UART BAUD RATE CONTROL REGISTER ................... 124 12.6 UART DATA BUFFER ........................125 13 INSTRUCTION TABLE ........................126 14 ELECTRICAL CHARACTERISTIC ....................127 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 6...
- Page 7 SN8P26L38 8-Bit Micro-Controller 14.1 ABSOLUTE MAXIMUM RATING ....................127 14.2 ELECTRICAL CHARACTERISTIC ....................127 15 DEVELOPMENT TOOL ........................128 15.1 SN8P26L38 EV- ..........................128 15.2 ICE EV-KIT APPLICATION NOTIC ..................129 16 OTP PROGRAMMING PIN ........................130 16.1 T : ..........130...
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Page 8: Product Overview
P-DIP 48 pins Powerful instructions LQFP 48 pins One clock per instruction cycle (1T) All ROM area JMP instruction. All ROM area CALL address instruction. All ROM area lookup table function (MOVC) Version 1.5 SONiX TECHNOLOGY CO., LTD Page 8... -
Page 9: System Block Diagram
TIMING GENERATOR CM0N Comparator 0 CM0O CM1P CM1N Comparator 1 CM1O SI, SO, SCK UART UTX, URX SYSTEM REGISTERS IR OUT IROUT INTERRUPT PWM 1 PWM1 CONTROL TIMER & COUNTER BUZZER 1 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 9... -
Page 10: Pin Assignment
P1.4 8 29 P4.7 P1.5 9 28 P4.6 P1.6 10 27 P4.5 P1.7 11 26 P4.4 P2.0 12 25 P4.3 13 14 15 16 17 18 19 20 21 22 23 24 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 10... -
Page 11: Pin Descriptions
P5.1: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. P5.1/SI Open-drain structure controlled by P1OC register. SI: SIO data input pin. P5.2/SO P5.2: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 11... -
Page 12: Pin Circuit Diagrams
P1OC Input Bus Output Output Bus Latch Open-Drain I/O Bus Input only pin shared with reset pin: OTP Program Mode OTP Vpp Input Input Bus Reset Trigger Reset Pin Code Option Version 1.5 SONiX TECHNOLOGY CO., LTD Page 12... - Page 13 CMnEN Input Bus Output Output Bus CMnOEN Latch Comparator Output General purpose I/O pin shared with external oscillator: Pull-Up Resistor PnUR Oscillator Code Option Input Bus Output Output Bus Latch Oscillator Version 1.5 SONiX TECHNOLOGY CO., LTD Page 13...
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Page 14: Central Processor Unit (Cpu)
The Interrupt vector is the head of interrupt service routine when any interrupt occurring. The General purpose area is main program area including main loop, sub-routines and data table. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 14... -
Page 15: Reset Vector(0000H)
Example: Defining Reset Vector ; 0000H START ; Jump to user program address. … START: ; 0010H, The head of user program. … ; User program … ENDP ; End of program Version 1.5 SONiX TECHNOLOGY CO., LTD Page 15... -
Page 16: Interrupt Vector(0008H)
RETI ; End of interrupt service routine … START: ; The head of user program. … ; User program … START ; End of user program … ENDP ; End of program Version 1.5 SONiX TECHNOLOGY CO., LTD Page 16... - Page 17 ; End of program. Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
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Page 18: Look-Up Table Description
Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Example: INC_YZ macro. INC_YZ MACRO INCMS ; Z+1 ; Not overflow INCMS ; Y+1 ; Not overflow ENDM Version 1.5 SONiX TECHNOLOGY CO., LTD Page 18... - Page 19 ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 … TABLE1: 0035H ; To define a word (16 bits) data. 5105H 2012H … Version 1.5 SONiX TECHNOLOGY CO., LTD Page 19...
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Page 20: Jump Table Description
; ACC = 3, jump to A3POINT SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size. - Page 21 SN8P26L38 8-Bit Micro-Controller Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”. ; “BUF0” is from 0 to 4. B0MOV A, BUF0 @JMP_A ; The number of the jump table listing is five. A0POINT ; ACC = 0, jump to A0POINT A1POINT ;...
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Page 22: Checksum Calculation
; If Not jump to checksum calculate CHECKSUM_END ; If Yes checksum calculated is done. Y_ADD_1: INCMS ; Increase Y ; Jump to checksum calculate CHECKSUM_END: … … END_USER_CODE: ; Label of program end Version 1.5 SONiX TECHNOLOGY CO., LTD Page 22... -
Page 23: Data Memory (Ram)
Bank 1 RAM directly. Under one bank condition and need to access the other bank RAM, setup the RBANK register is necessary. Sonix provides “Bank 0” type instructions (e.g. b0mov, b0add, b0bts1, b0bset…) to control Bank 0 RAM in non-zero RAM bank condition directly. -
Page 24: System Register
URBRC = UART baud rate control register. SIOM = SIO mode control register. SIOR = SIO clock rate control register. SIOB = SIO data buffer. STKP = Stack pointer buffer. STK0~STK7 = Stack 0 ~ stack 7 buffer. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 24... -
Page 25: Bit Definition Of System Register
S7PC11 S7PC10 S7PC9 S7PC8 STK7H 0F2H S6PC7 S6PC6 S6PC5 S6PC4 S6PC3 S6PC2 S6PC1 S6PC0 STK6L 0F3H S6PC12 S6PC11 S6PC10 S6PC9 S6PC8 STK6H 0F4H S5PC7 S5PC6 S5PC5 S5PC4 S5PC3 S5PC2 S5PC1 S5PC0 STK5L Version 1.5 SONiX TECHNOLOGY CO., LTD Page 25... - Page 26 3. One-bit name had been declared in SN8ASM assembler with “F” prefix code. 4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers. 5. For detail description, please refer to the “System Register Quick Reference Table” Version 1.5 SONiX TECHNOLOGY CO., LTD Page 26...
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Page 27: Accumulator
“PUSH”, “POP” save and load ACC, PFLAG data into buffers. Example: Protect ACC and working registers. INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 27... -
Page 28: Program Flag
1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero. Note: Refer to instruction set table for detailed information of C, DC and Z flags. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 28... -
Page 29: Program Counter
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. CMPRS A, #12H ; To skip, if ACC = 12H. C0STEP ; Else jump to C0STEP. … … C0STEP: Version 1.5 SONiX TECHNOLOGY CO., LTD Page 29... - Page 30 DECS BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: DECMS instruction: DECMS BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: Version 1.5 SONiX TECHNOLOGY CO., LTD Page 30...
- Page 31 ; If ACC = 0, jump to A0POINT A1POINT ; ACC = 1, jump to A1POINT A2POINT ; ACC = 2, jump to A2POINT A3POINT ; ACC = 3, jump to A3POINT … … Version 1.5 SONiX TECHNOLOGY CO., LTD Page 31...
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Page 32: H, L Registers
; Clear @HL to be zero ; L – 1, if L = 0, finish the routine DECMS CLR_HL_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … … Version 1.5 SONiX TECHNOLOGY CO., LTD Page 32... -
Page 33: Y, Z Registers
; Clear @YZ to be zero ; Z – 1, if Z= 0, finish the routine DECMS CLR_YZ_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … Version 1.5 SONiX TECHNOLOGY CO., LTD Page 33... -
Page 34: R Registers
Bit 2 Bit 1 Bit 0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Read/Write After reset Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 34... -
Page 35: Addressing Mode
; To clear Y register to access RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 35... -
Page 36: Stack Operation
STKP = 5 STK5H STK5L STKP STKP STKP = 4 STK4H STK4L STKP = 3 STK3H STK3L STKP = 2 STK2H STK2L STKP = 1 STK1H STK1L STKP = 0 STK0H STK0L Version 1.5 SONiX TECHNOLOGY CO., LTD Page 36... -
Page 37: Stack Registers
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKnL SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0 Read/Write After reset STKn = STKnH , STKnL (n = 7 ~ 0) Version 1.5 SONiX TECHNOLOGY CO., LTD Page 37... -
Page 38: Stack Operation Example
STKP Register Stack Buffer Stack Level Description STKPB2 STKPB1 STKPB0 High Byte Low Byte STK7H STK7L STK6H STK6L STK5H STK5L STK4H STK4L STK3H STK3L STK2H STK2L STK1H STK1L STK0H STK0L Free Free Version 1.5 SONiX TECHNOLOGY CO., LTD Page 38... -
Page 39: Code Option Table
P02: Set reset pin to general purpose input only pin (P0.2). The external reset function is disable and the pin is input pin. 2.5.2 SECURITY CODE OPTION Security code option is OTP ROM protection. When enable security code option, the ROM code is secured and not dumped complete ROM contents. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 39... -
Page 40: Reset
High Detect Low Detect Watchdog Overflow Watchdog Normal Run Watchdog Reset Watchdog Stop System Normal Run System Status System Stop Power On External Watchdog Delay Time Reset Delay Reset Delay Time Time Version 1.5 SONiX TECHNOLOGY CO., LTD Page 40... -
Page 41: Power On Reset
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the watchdog timer function. Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 41... -
Page 42: Brown Out Reset
DC low battery condition. When turn off the AC power, the VDD drops slowly and through the dead-band for a while. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 42... -
Page 43: The System Operating Voltage
Delay Time The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by each MCU. - Page 44 1. After any LVD reset, LVD24, LVD28 flags are cleared. 2. The voltage level of LVD 2.4V or 2.8V is for design reference only. Don’t use the LVD indicator as precision VDD measurement. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 44...
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Page 45: Brown Out Reset Improvement
IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead-band. The external reset information is described in the next section. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 45... -
Page 46: External Reset
The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference. Note: The reset circuit is no any protection against unusual power or brown out reset. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 46... -
Page 47: Diode & Rc Reset Circuit
PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener specification. Select the right zener voltage to conform the application. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 47... -
Page 48: Voltage Bias Reset Circuit
When power drops below the reset detect voltage, the system reset would be triggered, and then system executes reset sequence. That makes sure the system work well under unstable power situation. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 48... -
Page 49: External Reset Ic
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can improve all power variation. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 49... -
Page 50: System Clock
Fcpu of slow mode is fixed Flosc/4 condition. In high noisy environment, below “Fhosc/4” of Fcpu code option is the strongly recommendation to reduce high frequency noise effect. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 50... -
Page 51: Oscm Register
8M X’tal: The system clock source is from external high speed crystal/resonator. The oscillator bandwidth is 8MHz~16MHz. 4M X’tal: The system clock source is from external high speed crystal/resonator. The oscillator bandwidth is 1MHz~10MHz. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 51... -
Page 52: Internal High Rc
High_Clk code option. The start up time of crystal/ceramic and RC type oscillator is different. RC type oscillator’s start-up time is very short, but the crystal’s is longer. The oscillator start-up time decides reset time length. 4MHz Crystal 32768Hz Crystal 4MHz Ceramic Version 1.5 SONiX TECHNOLOGY CO., LTD Page 52... -
Page 53: Crystal/Ceramic
“R” value is to change frequency. 50P~100P is good value for “C”. XOUT pin is general purpose I/O pin. Note: Connect the R and C as near as possible to the VDD pin of micro-controller. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 53... -
Page 54: External Clock Signal
XIN pin. XOUT pin is general purpose I/O pin. External Clock Input XOUT Note: The GND of external oscillator circuit must be as near as possible to VSS pin of micro-controller. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 54... -
Page 55: System Low Clock
; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P0.0 ; Measure the Fcpu frequency by oscilloscope. Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC frequency. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 55... -
Page 56: System Operation Mode
P0, P1, T0 Wakeup source P0, P1, Reset Reset EHOSC: External high clock IHRC: Internal high clock (8M RC oscillator) ILRC: Internal low clock (10K RC oscillator at 3V) Version 1.5 SONiX TECHNOLOGY CO., LTD Page 56... -
Page 57: Normal Mode
Note: If the system is in normal mode, to set STPHX=1 to disable the high clock oscillator. The system is under no system clock condition. This condition makes the system stay as power down mode, and can be wake-up by P0, P1 level change trigger. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 57... -
Page 58: Green Mode
The green mode wake-up source are P0, P1 level change trigger and unique time overflow. Note: Sonix provides “GreenMode” macro to control green mode operation. It is necessary to use “@GreenMode” macro to control system inserting green mode. The macro includes three instructions. Please take care the macro length as using BRANCH type instructions, e.g. - Page 59 Example: Switch normal/slow mode to green mode and enable T0 wake-up function with RTC. ; Clear T0 counter. B0BSET FT0ENB ; To enable T0 timer ; Go into green mode ; Declare “GreenMode” macro directly. GreenMode Version 1.5 SONiX TECHNOLOGY CO., LTD Page 59...
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Page 60: Wakeup
The wakeup time is as the following. The wakeup time = 1/Fosc * 2048 = 0.512 ms (Fosc = 4MHz) The total wakeup time = 0.512 ms + oscillator start-up time Version 1.5 SONiX TECHNOLOGY CO., LTD Page 60... -
Page 61: P1W Wakeup Control Register
Bit 0 P17W P16W P15W P14W P13W P12W P11W P10W Read/Write After reset Bit[7:0] P10W~P17W: Port 1 wakeup function control bits. 0 = Disable P1n wakeup function. 1 = Enable P1n wakeup function. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 61... -
Page 62: Interrupt
Global Interrupt Request Signal 2-Bit Gating CM0IRQ Comparator 0 Trigger Latchs CM1IRQ Comparator 1 Trigger TXIRQ UART Transmit End RXIRQ UART Receive End Note: The GIE bit must enable during all interrupt operation. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 62... -
Page 63: Inten Interrupt Enable Register
0 = Disable comparator 0 interrupt function. 1 = Enable comparator 0 interrupt function. CM1IEN (CM1M’s bit 6): Comparator 1 interrupt control bit. 0 = Disable comparator 1 interrupt function. 1 = Enable comparator 1 interrupt function. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 63... -
Page 64: Intrq Interrupt Request Register
0 = None comparator 0 interrupt request. 1 = Comparator 0 interrupt request. CM1IRQ (CM1M’s bit 5): Comparator 1 interrupt request flag. 0 = None comparator 1 interrupt request. 1 = Comparator 1 interrupt request. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 64... -
Page 65: Gie Global Interrupt Operation
0 = Disable global interrupt. 1 = Enable global interrupt. Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE Note: The GIE bit must enable during all interrupt operation. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 65... -
Page 66: Push, Pop Routine
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine executed. START INT_SERVICE START: … INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector … ENDP Version 1.5 SONiX TECHNOLOGY CO., LTD Page 66... -
Page 67: External Interrupt Operation (Int0)
EXTERNAL INTERRUPT OPERATION (INT0) Sonix provides 1 external interrupt sources in the micro-controller. INT0 is external interrupt trigger source and builds in edge trigger configuration function. When the external edge trigger occurs, the external interrupt request flag will be set to “1”... -
Page 68: Int1 (P0.1) Interrupt Operation
; P01IRQ = 0, exit interrupt vector B0BCLR FP01IRQ ; Reset P01IRQ … ; INT1 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 68... -
Page 69: T0 Interrupt Operation
A, #74H B0MOV T0C, A ; Reset T0C. … ; T0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 69... - Page 70 … ; The time must be longer than 16us. B0BCLR FT0IRQ ; Reset T0IRQ … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 70...
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Page 71: T1 Interrupt Operation
A, T1C B0MOV T1CBUF, A ; Save pulse width. … ; T1 interrupt service routine … EXIT_INT: ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 71... -
Page 72: Tc1 Interrupt Operation
A, #74H B0MOV TC1C, A ; Reset TC1C. … ; TC1 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 72... -
Page 73: Comparator Interrupt Operation (Cmp0, Cmp1)
6.11 COMPARATOR INTERRUPT OPERATION (CMP0, CMP1) Sonix provides 2 sets comparator with interrupt function in the micro-controller. The comparator interrupt trigger edge direction is the rising edge of comparator output . When the comparator output status transition occurs, the comparator interrupt request flag will be set to “1”... -
Page 74: Sio Interrupt Operation
; SIOIRQ = 0, exit interrupt vector B0BCLR FSIOIRQ ; Reset SIOIRQ … ; SIO interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 74... -
Page 75: Uart Interrupt Operation
; RXIRQ = 0, exit interrupt vector B0BCLR FRXIRQ ; Reset RXIRQ … ; UART receive interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 75... -
Page 76: Multi-Interrupt Operation
B0BTS0 FSIOIRQ ; Check SIOIRQ INTSIO ; Jump to SIO interrupt service routine … … INT_EXIT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 76... -
Page 77: O Port
CM1EN=1, CM1OEN=1 P3.2 URXEN=1. P3.3 UTXEN=1. P5.0 SENB=1. P5.1 SENB=1. P5.2 SENB=1. P5.3 BZ1/PWM1 TC1ENB=1, TC1OUT=1 or PWM1OUT=1 P5.4 IROUT IREN=1 * DC: Digital Characteristic. AC: Analog Characteristic. HV: High Voltage Characteristic. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 77... -
Page 78: I/O Port Mode
; Set all ports to be output mode. B0MOV P0M, A B0MOV P1M, A B0MOV P5M, A B0BCLR P1M.2 ; Set P1.2 to be input mode. B0BSET P1M.2 ; Set P1.2 to be output mode. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 78... -
Page 79: I/O Pull Up Register
Note: P0.2 is input only pin and without pull-up resister. The P0UR.2 keeps “1”. Example: I/O Pull up Register A, #0FFH ; Enable Port0, 1, 5 Pull-up register, B0MOV P0UR, A B0MOV P1UR, A B0MOV P5UR, A Version 1.5 SONiX TECHNOLOGY CO., LTD Page 79... -
Page 80: I/O Open-Drain Register
P51OC: P5.1 open-drain control bit 0 = Disable open-drain mode 1 = Enable open-drain mode Bit 7 P52OC: P5.2 open-drain control bit 0 = Disable open-drain mode 1 = Enable open-drain mode Version 1.5 SONiX TECHNOLOGY CO., LTD Page 80... - Page 81 Example: Disable P1.0 to open-drain mode and output low. A, #0 ; Disable P1.0 open-drain function. B0MOV P1OC, A Note: After disable P1 open-drain function, P1 mode returns to last I/O mode. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 81...
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Page 82: I/O Port Data Register
Example: Write one bit data to output port. ; Set P1.3 and P5.4 to be “1”. B0BSET P1.3 B0BSET P5.4 ; Set P1.3 and P5.4 to be “0”. B0BCLR P1.3 B0BCLR P5.4 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 82... -
Page 83: Timers
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the main routine of the program. Main: A, #5AH ; Clear the watchdog timer. B0MOV WDTR, A … … CALL SUB1 CALL SUB2 … … MAIN Version 1.5 SONiX TECHNOLOGY CO., LTD Page 83... - Page 84 ; I/O and RAM are correct. Clear watchdog timer and ; execute program. A, #5AH ; Clear the watchdog timer. B0MOV WDTR, A … CALL SUB1 CALL SUB2 … … … MAIN Version 1.5 SONiX TECHNOLOGY CO., LTD Page 84...
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Page 85: Timer 0 (T0)
The delay is about 16us and use T0 interrupt service routine executing time to be the 16us delay time. 2. In RTC mode, the T0 interval time is fixed at 0.5 sec and T0C is 256 counts. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 85... -
Page 86: T0M Mode Register
T0ENB: T0 counter control bit. 0 = Disable T0 timer. 1 = Enable T0 timer. Note: T0RATE is not available in RTC mode. The T0 interval time is fixed at 0.5 sec. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 86... -
Page 87: T0C Counting Register
488.281 us Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us Note: In RTC mode, T0C is 256 counts and generatesT0 0.5 sec interval time. Don’t change T0C value in RTC mode. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 87... -
Page 88: T0 Timer Operation Sequence
Set T0 interrupt interval time. A,#7FH B0MOV T0C,A ; Set T0C value. Set T0 timer function mode. B0BSET FT0IEN ; Enable T0 interrupt function. Enable T0 timer. B0BSET FT0ENB ; Enable T0 timer. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 88... -
Page 89: Timer 1 (T1)
0 = Disable T1 timer. 1 = Enable T1 timer. Bit [6:4] T1RATE[2:0]: T1 timer internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. … 110 = fcpu/4. 111 = fcpu/2. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 89... -
Page 90: T1Ch, T1Cl Counting Register
16 us 128 s 1953.125 us Fcpu/8 524.288 ms 8 us 64 s 976.563 us Fcpu/4 262.144 ms 4 us 31 s 488.281 us Fcpu/2 131.072 ms 2 us 16 s 244.141 us Version 1.5 SONiX TECHNOLOGY CO., LTD Page 90... - Page 91 ; Write “0” into T1CL to clear T1CL. B0MOV T1CL, A … B0MOV T1CH, A ; Write T1CH data and T1CH, T1CL are imported to T1C ; 16-bit buffer. Note: Don’t clear T1CL by “CLR” instruction. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 91...
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Page 92: T1 Timer Operation Sequence
; Set T1CL value. A,#7FH B0MOV T1CH,A ; Set T1CH value. Set T1 timer function mode. B0BSET FT1IEN ; Enable T1 interrupt function. Enable T1 timer. B0BSET FT1ENB ; Enable T1 timer. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 92... -
Page 93: Timer/Counter 0 (Tc1)
TC1 / 2 P5.3 TC1R Reload ALOAD1, TC1OUT Data Buffer TC1 Rate (Fcpu/2~Fcpu/256) PWM1OUT Compare TC1CKS TC1ENB Fcpu Load TC1C 8-Bit Binary Up TC1 Time Out Counting Counter INT1 (Schmitter Trigger) CPUM0,1 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 93... -
Page 94: Tc1M Mode Register
1 = Enable TC1 timer. Note: When TC1CKS=1, TC1 became an external event counter and TC1RATE is useless. No more P0.1 interrupt request will be raised. (P0.1IRQ will be always 0). Version 1.5 SONiX TECHNOLOGY CO., LTD Page 94... -
Page 95: Tc1C Counting Register
16 us 500 ms 1953.125 us Fcpu/8 2.048 ms 8 us 250 ms 976.563 us Fcpu/4 1.024 ms 4 us 125 ms 488.281 us Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us Version 1.5 SONiX TECHNOLOGY CO., LTD Page 95... -
Page 96: Tc1R Auto-Load Register
TC1R initial value = N - (TC1 interrupt interval time * input clock) = 256 - (10ms * 4MHz / 4 / 64) = 256 - (10 * 4 * 10 / 4 / 64) = 100 = 64H Version 1.5 SONiX TECHNOLOGY CO., LTD Page 96... -
Page 97: Tc1 Clock Frequency Output (Buzzer)
; Enable TC1 output to P5.3 and disable P5.3 I/O function B0BSET FALOAD1 ; Enable TC1 auto-reload function B0BSET FTC1ENB ; Enable TC1 timer Note: Buzzer output is enable, and “PWM1OUT” must be “0”. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 97... -
Page 98: Tc1 Timer Operation Sequence
Set TC1 timer function mode. B0BSET FTC1IEN ; Enable TC1 interrupt function. B0BSET FTC1OUT ; Enable TC1OUT (Buzzer) function. B0BSET FPWM1OUT ; Enable PWM function. Enable TC1 timer. B0BSET FTC1ENB ; Enable TC1 timer. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 98... -
Page 99: Pwm1 Mode
125K Overflow per 16 count The Output duty of PWM is with different TC1R. Duty range is from 0/256~255/256. …… …… …… …… TC1 Clock TC1R=00H High TC1R=01H High TC1R=80H High TC1R=FFH Version 1.5 SONiX TECHNOLOGY CO., LTD Page 99... -
Page 100: Tc1Irq And Pwm Duty
PWM duty. TC1 Overflow, TC1IRQ = 1 0xFF TC1C Value 0x00 PWM1 Output (Duty Range 0~255) PWM1 Output (Duty Range 0~63) PWM1 Output (Duty Range 0~31) PWM1 Output (Duty Range 0~15) Version 1.5 SONiX TECHNOLOGY CO., LTD Page 100... -
Page 101: Pwm Program Example
TC1R, A INCMS BUF0 ; Get the new TC1R value from the BUF0 buffer defined by ; programming. B0MOV A, BUF0 B0MOV TC1R, A Note: The PWM can work with interrupt request. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 101... -
Page 102: Pwm1 Duty Changing Notice
Above diagram is shown the waveform with fixed TC1R. In every TC1C overflow PWM output “High, when TC1C≧ TC1R PWM output ”Low”. Note: Setting PWM duty in program processing must be at the new cycle start. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 102... - Page 103 … B0BTS1 FTC1IRQ INT_SER90 B0MOV A, TC1RBUF ; When TC1 Interrupt occurs, update TC1R. B0MOV TC1R, A … … INT_SER90: … ; Pop routine to load ACC and PFLAG from buffers. RETI Version 1.5 SONiX TECHNOLOGY CO., LTD Page 103...
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Page 104: Analog Comparator
CM1N: Comparator 1 negative input pin shared with P2.5. CM1N enables when CM1EN=1. CM1O: Comparator 1 output pin shared with P2.7. CM1O enables when CM1EN=1 and CM1OEN = 1. The comparator pins are GPIO mode except above conditions. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 104... - Page 105 Note: The comparator output pin signal is through internal buffer and not pure analog comparator output. The comparator negative input pin and positive input pin must be connected 0.1uF capacitor to ground and closer to comparator pins. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 105...
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Page 106: Cmp0M Register
1 = CM0P voltage or comparator 0 reference voltage is larger than CM0N voltage. Bit[1:0] CMS[1:0]: Comparator internal reference voltage select bit. 00 = 0.9V, 01 = 1.0V, 10 = 1.1V, 11 = 1.2V Version 1.5 SONiX TECHNOLOGY CO., LTD Page 106... -
Page 107: Cmp1M Register
1 = CM1P voltage or comparator 1 reference voltage is larger than CM1N voltage. Note: CMnOUT is comparator raw output without latch. It varies depend on the comparator process result. But the CMnIRQ is latch comparator output result. It must be cleared by program. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 107... -
Page 108: Analog Comparator Application
; Set internal reference voltage = 1.0V. B0BSET FCMS0 ; Delay 2 instructions cycle to be the internal band-gap ; setup time. B0BTS1 FCM1OUT ; Check comparator 1 status through CM1OUT flag. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 108... - Page 109 ; Is no battery status, go to no battery routine. ; Low battery process. LowBat: … … Main ; Return to main loop. ; No battery process. NoBat: … … Main ; Return to main loop. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 109...
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Page 110: Ir Output
System loads IRR into IRC automatically and next cycle starts. Up Counting Reload Value Output Low IREN IRR Reload Data Buffer Data Buffer IROUT pin Compare IR Signal CREN Load IRC Overflow Fhosc 8-Bit Binary Up Counting Counter CPUM0 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 110... -
Page 111: Ir Control Register
Bit 2 Bit 1 Bit 0 IRC7 IRC6 IRC5 IRC4 IRC3 IRC2 IRC1 IRC0 Read/Write After reset Note: Set IRC=IRR before IR output enable to make sure the first cycle correct. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 111... -
Page 112: Irr Auto-Load Register
IRR initial value = 256 - (IR interrupt interval time * input clock) IR interval time = 1/38KHz = 26.3us Input clock = external oscillator 4MHz. IRR = 256 - (26.3us * 4MHz) = 150.8 ≈ 151 = 97h Version 1.5 SONiX TECHNOLOGY CO., LTD Page 112... -
Page 113: Ird Ir Duty Control Register
1/2 duty 1/3 duty 1/4duty (KHz) Rate 193.50 172.67 162.25 0.00% 200.50 182.00 172.75 0.10% 203.50 186.00 177.25 0.25% 39.2 205.00 188.00 179.50 0.04% 206.00 189.33 181.00 0.00% 220.50 208.67 202.75 0.60% Version 1.5 SONiX TECHNOLOGY CO., LTD Page 113... -
Page 114: Ir Output Operation Sequence
A, #IRDUTYVAL ;IRD value for IR duty. IRD, A Enable IR output. BSET FIREN ; Set IROUT pin to IR carry output function. BSET FCREN ; Set IR carry signal output. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 114... -
Page 115: Serial Input/Output Transceiver (Sio)
CPUM1,0 SENB SCLKMD CPOL CPHA SIO Time Out SIO 3-bit I/O Counter CPUM1,0 START SENB ÷1 ÷8 Fcpu SIO 8-bit Counter ÷16 ÷32 Auto-Reload CPUM1,0 SIOR Register Srate1,0 SIO Interface Circuit Diagram Version 1.5 SONiX TECHNOLOGY CO., LTD Page 115... - Page 116 SCK idle status = High. The transfer first bit = LSB. SCK data transfer edge = Falling bit0 bit1 bit2 bit3 bit4 bit5 bit6 Bit7 Next data edge. SIO Data Transfer Timing Version 1.5 SONiX TECHNOLOGY CO., LTD Page 116...
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Page 117: Siom Mode Register
CPHA: The Clock Phase bit controls the phase of the clock on which data is sampled. 0 = Data receive at the first clock phase. 1 = Data receive at the second clock phase. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 117... -
Page 118: Siob Data Buffer
(SCKMD = 1) Read SIOB Read SIOB 2nd Receive Buffer 2nd Receive Buffer (Address = SIOB) (Address = SIOB) Write SIOB Write SIOB Shift Register Shift Register (SIOB) (SIOB) SIO Data Transfer Diagram Version 1.5 SONiX TECHNOLOGY CO., LTD Page 118... -
Page 119: Sior Register Description
Example: Setup the SIO clock to be 5KHz. Fosc = 4MHz. SIO’s rate = Fcpu = Fosc/4. SIOR = 256 – (1/(2*5KHz) * 4MHz/4) = 256 – (0.0001*1000000) = 256 – 100 = 156 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 119... -
Page 120: Universal Asynchronous Receiver/Transmitter (Uart)
The UART interface is an universal asynchronous receiver/transmitter method. The serial interface is applied to low speed data transfer and communicate with low speed peripheral devices. The UART transceiver of Sonix 8-bit MCU allows RS232 standard and supports one and two bytes data length. The transfer format has start bit, 8/16-bit data, parity bit and stop bit. - Page 121 The stop bit is like start bit using a simple format to indicate the end of UART transfer. The stop bit format is low to high edge change and the duration is one bit period. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 121...
- Page 122 TXIEN=0, but cleared by program. When UART operation finished, the RXIRQ/TXIRQ would be set to “1”. Note: The first step of UART operation is to setup the UART pins’ mode. Enable URXEN/UTXEN to control UART pins’ mode. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 122...
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Page 123: Uart Receiver Control Register
0 = UART TX parity bit format is even parity. 1= UART TX parity bit format is odd parity. Bit 1 UTXM: UART TX data buffer length control bit. 0 = 1-byte. 1 = 2-byte. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 123... -
Page 124: Uart Baud Rate Control Register
01100 0.16% 00110 -6.99% 51200 10010 2.80% 01001 -2.34% 00100 -2.34% 57600 10000 2.12% 01000 -3.55% 00011 8.51% 102400 01001 -2.34% 00100 -2.34% 00010 -18.62% 115200 01000 -3.55% 00011 8.51% 00001 8.51% Version 1.5 SONiX TECHNOLOGY CO., LTD Page 124... -
Page 125: Uart Data Buffer
After Reset Bit[7:0] URRXD2: UART received data buffer byte 2. UART Data Mode URTXD2 URTXD1 URRXD2 URRXD1 1-byte 0x00 1-byte data 0x00 1-byte data 2-byte High-byte data Low-byte data High-byte data Low-byte data Version 1.5 SONiX TECHNOLOGY CO., LTD Page 125... -
Page 126: Instruction Table
Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1. 2. If branch condition is true then “S = 1”, otherwise “S = 0”. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 126... -
Page 127: Electrical Characteristic
Low voltage reset level. Fcpu = 1 MHz. LVD Voltage Vdet1 Low voltage indicator level. Fcpu = 1 MHz. Vdet2 Low voltage indicator level. Fcpu = 1 MHz *These parameters are for design reference, not tested. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 127... -
Page 128: Development Tool
8-Bit Micro-Controller DEVELOPMENT TOOL SONIX provides ICE (in circuit emulation), IDE (Integrated Development Environment) and EV-kit for SN8P26L38 development. ICE and EV-kit are external hardware devices, and IDE is a friendly user interface for firmware development and emulation. These development tools’ version is as following. -
Page 129: Ice And Ev-Kit Application Notic
ICE and EV-KIT APPLICATION NOTIC SN8P26L38 EV-kit includes comparator emulation module. There is a SN8P26L38P chip programmed emulating code to emulate comparator function. The SN8P26L38 comparator pins are shared with P2 GPIO pins. In ICE environment, the comparator pins isn’t connected with GPIO pin. -
Page 130: Otp Programming Pin
JP1 for MP transition board DIP12 DIP38 DIP13 DIP36 DIP14 DIP35 DIP15 DIP34 DIP16 DIP33 DIP17 DIP32 DIP18 DIP31 DIP19 DIP30 DIP20 DIP29 DIP21 DIP28 DIP22 DIP27 DIP23 DIP26 DIP24 DIP25 JP3 for MP transition board Version 1.5 SONiX TECHNOLOGY CO., LTD Page 130... -
Page 131: Programming Pin Mapping
SN8P26L38 8-Bit Micro-Controller 16.2 Programming Pin Mapping: Programming Information of SN8P26L38 Chip Name SN8P26L38P SN8P26L38F EZ Writer OTP IC / JP3 Pin Assignment Connector Number Name Number Number Number Number 27,48 21,42 1,26 20,43 P5.0 P5.0 P1.0 P1.0 P5.1 P5.1 P1.1,... -
Page 132: Marking Definition
Marking Definition 17.1 INTRODUCTION There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit MCU for order or obtain information. This definition is only for Blank OTP MCU. 17.2 MARKING INDETIFICATION SYSTEM SN8 X Part No. -
Page 133: Marking Example
..9=09 A=10 B=11 ..1=January Month 2=February ..9=September A=October B=November C=December 03= 2003 Year 04= 2004 05= 2005 06= 2006 ..Version 1.5 SONiX TECHNOLOGY CO., LTD Page 133... -
Page 134: Package Information
2.550 60.960 62.230 64.770 0.600 15.240 0.540 0.545 0.550 13.716 13.843 13.970 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.630 0.650 0.067 16.002 16.510 1.702 θ° 0° 7° 15° 0° 7° 15° Version 1.5 SONiX TECHNOLOGY CO., LTD Page 134... -
Page 135: Lqfp 48 Pin
0.354 BSC 9.00 BSC 0.276 BSC 7.00 BSC 0.354 BSC 9.00 BSC 0.276 BSC 7.00 BSC 0.020 BSC 0.5 BSC 0.007 0.011 0.17 0.27 0.018 0.030 0.45 0.75 0.039 REF 1 REF Version 1.5 SONiX TECHNOLOGY CO., LTD Page 135... - Page 136 SONIX product could create a situation where personal injury or death may occur.
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