Table of Contents
Advertisement
Quick Links
SN8P2200 Series
USER'S MANUAL
SN8P2204
SN8P2203
SN8P2202
SN8P22021
SN8P2201
S
O
N
i
X
S
O
N
i
X
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
8
-
B
i
t
M
i
8
-
B
i
t
M
i
c
r
o
-
C
o
n
c
r
o
-
C
o
n
Page 1
SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
t
r
o
l
l
e
r
t
r
o
l
l
e
r
Version 1.7
Advertisement
Table of Contents
Related Manuals for SONIX SN8P2203
Summary of Contents for SONIX SN8P2203
- Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.
-
Page 2: Amendment History
VREG voltage will between 3.1 ~ 3.5 volts. VER1.5 Feb.2008 1. Modify the 9.5.10 the USTATUS register bit 6’s description. 2. Add chapter 16 marking definition VER1.6 Mar. 2008 Add SN8P22021 VER1.7 May. 2008 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 2... -
Page 3: Table Of Contents
2.2.2 DIRECTLY ADDRESSING MODE ....................36 2.2.3 INDIRECTLY ADDRESSING MODE ..................... 36 2.3 STACK OPERATION..........................37 2.3.1 OVERVIEW ............................. 37 2.3.2 STACK REGISTERS ........................38 2.3.3 STACK OPERATION EXAMPLE....................39 3 RESET ................................40 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 3... - Page 4 6.2 INTEN INTERRUPT ENABLE REGISTER ..................59 6.3 INTRQ INTERRUPT REQUEST REGISTER..................60 6.4 GIE GLOBAL INTERRUPT OPERATION ..................60 6.5 PUSH, POP ROUTINE........................... 61 6.6 INT0 (P0.0) INTERRUPT OPERATION....................62 6.7 T0 INTERRUPT OPERATION......................64 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 4...
- Page 5 8.5.4 Tn TIMER CAPTURE OPERATION....................92 8.5.5 Tn INPUT PERIOD MEASUREMENT ................... 93 8.5.6 Tn INPUT PULSE WIDTH MEASUREMENT ................95 9 UNIVERSAL SERIAL BUS (USB) ......................97 9.1 OVERVIEW ............................97 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 5...
- Page 6 14 OTP PROGRAMMING PIN........................118 14.1 THE PIN ASSIGNMENT OF EASY WRITER TRANSITION BOARD SOCKET......118 14.2 PROGRAMMING PIN MAPPING....................119 15 PACKAGE INFORMATION ........................ 120 15.1 SK-DIP 28 PIN ........................... 120 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 6...
- Page 7 15.13 SSOP 16 PIN............................. 132 15.14 QFN 16 PIN ............................133 16 MARKING DEFINITION........................134 16.1 INTRODUCTION ..........................134 16.2 MARKING INDETIFICATION SYSTEM ..................134 16.3 MARKING EXAMPLE........................135 16.4 DATECODE SYSTEM ........................135 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 7...
-
Page 8: Product Overview
Features Selection Table TIMER WAKE-UP CHIP ROM RAM STACK T0 TC0 T1 T2 PS/2 BZ I/O PACKAGE PIN NO. SN8P2204 6K*16 256*8 SKDIP28/SOP28/SSOP28 SN8P2203 6K*16 256*8 SKDIP24/SOP24/SSOP24 SN8P2202 6K*16 256*8 PDIP18/SOP18/SSOP20 SN8P22021 6K*16 256*8 SOP20 SN8P2201 6K*16 256*8 PDIP14/SOP14/SSOP16/QFN16 Version 1.7 SONiX TECHNOLOGY CO., LTD... -
Page 9: System Block Diagram
HIGH OSC. LOW RC FLAGS 3.3v REGULATOR VREG TIMING GENERATOR USB ENGINE PS2_1 SCLK PS2_1 SDATA SYSTEM REGISTERS PS2_2 SCLK INTERRUPT PS2_2 SDATA CONTROL TIMER & COUNTER BUZZER 0 PWM 0 BUZZER0 PWM0 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 9... -
Page 10: Pin Assignment
SN8P2203S (SOP 24 pins) SN8P2203X (SSOP 24 pins) P1.0 P5.4/BZ0/PWM0 P1.1 P5.3 P1.5 P5.2 P1.6 P5.1 P1.7 P5.0 P0.2/T2IN P5.5 P0.1/T1IN P5.6 P0.0/INT0 P5.7 D+/SCLK P1.4/RST/VPP D-/SDATA VREG P1.3/XIN P1.2/XOUT SN8P2203K SN8P2203S SN8P2203X Version 1.7 SONiX TECHNOLOGY CO., LTD Page 10... - Page 11 P0.0/INT0 P5.0 D+/SCLK P1.4/RST/VPP D-/SDATA VREG P1.3/XIN P1.2/XOUT SN8P2202X SN8P22021S (SOP 20 pins) P1.1 P1.0 P1.5 P5.4/BZ0/PWM0 P1.6 P5.3 P0.2/T2IN P5.2 P0.1/T1IN P5.1 P0.0/INT0 P5.0 D+/SCLK P1.4/RST/VPP D-/SDATA VREG P1.3/XIN P1.2/XOUT SN8P22021S Version 1.7 SONiX TECHNOLOGY CO., LTD Page 11...
- Page 12 P1.4/RST/VPP D-/SDATA VREG P1.3/XIN P1.2/XOUT SN8P2201X 16 15 14 13 P1.0 1 ● 12 D+/SCLK P1.1 2 11 D-/SDATA SN8P2201J P0.1 3 10 VDD P0.0/INT0 4 9 P1.2/XOUT 5 6 7 8 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 12...
-
Page 13: Pin Descriptions
P5[7:2] Schmitt trigger structure and built-in pull-up resisters as input mode. VREG 3.3V voltage output from USB 3.3V regulator. D+, D- USB differential data line. SCLK, SDATA PS/2 clock and data lines. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 13... -
Page 14: Pin Circuit Diagrams
Latch Open-Drain P1OC Port 1.2, 1.3 structure: Pull-Up Oscillator PnM, PnUR Code Option Input Bus Output Output Bus Latch Int. Osc. Port 1.4 structure: Ext. Reset Code Option Int. Bus Int. Rst Version 1.7 SONiX TECHNOLOGY CO., LTD Page 14... -
Page 15: Central Processor Unit (Cpu)
Jump to user start address 0001H General purpose area 0007H 0008H User interrupt vector Interrupt vector 0009H User program 000FH 0010H 0011H General purpose area 17FCH End of user program 17FDH 17FEH Reserved 17FFH Version 1.7 SONiX TECHNOLOGY CO., LTD Page 15... -
Page 16: Reset Vector (0000H)
Example: Defining Reset Vector ; 0000H START ; Jump to user program address. … START: ; 0010H, The head of user program. … ; User program … ENDP ; End of program Version 1.7 SONiX TECHNOLOGY CO., LTD Page 16... -
Page 17: Interrupt Vector (0008H)
RETI ; End of interrupt service routine … START: ; The head of user program. … ; User program … START ; End of user program … ENDP ; End of program Version 1.7 SONiX TECHNOLOGY CO., LTD Page 17... - Page 18 ENDP ; End of program. Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
-
Page 19: Look-Up Table Description
Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Example: INC_YZ macro. INC_YZ MACRO INCMS ; Z+1 ; Not overflow INCMS ; Y+1 ; Not overflow ENDM Version 1.7 SONiX TECHNOLOGY CO., LTD Page 19... - Page 20 ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 … TABLE1: 0035H ; To define a word (16 bits) data. 5105H 2012H … Version 1.7 SONiX TECHNOLOGY CO., LTD Page 20...
-
Page 21: Jump Table Description
; ACC = 3, jump to A3POINT SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size. - Page 22 SN8P2200 Series USB 1.1 Low-Speed 8-Bit Micro-Controller Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”. B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A ; The number of the jump table listing is five. A0POINT ; ACC = 0, jump to A0POINT A1POINT ;...
-
Page 23: Checksum Calculation
; If Not jump to checksum calculate CHECKSUM_END ; If Yes checksum calculated is done. Y_ADD_1: INCMS ; Increase Y ; Jump to checksum calculate CHECKSUM_END: … … END_USER_CODE: ; Label of program end Version 1.7 SONiX TECHNOLOGY CO., LTD Page 23... -
Page 24: Code Option Table
Enable P1.4 input only without pull-up resister. Enable Enable ROM code Security function. Security Disable Disable ROM code Security function. Fcpu code option is only available for High Clock. Fcpu of slow mode is Flosc/4. Note: Version 1.7 SONiX TECHNOLOGY CO., LTD Page 24... -
Page 25: Data Memory (Ram)
80h~FFh of Bank 0 store system registers (128 “ bytes). “ System register “ “ “ 0FFh End of bank 0 area 100h BANK1 “ “ BANK1 General purpose area “ “ “ 17Fh Version 1.7 SONiX TECHNOLOGY CO., LTD Page 25... -
Page 26: System Register
TC0C = TC0 counting register. @YZ = RAM YZ indirect addressing index pointer. PnUR = Port n pull-up resister control register. STK0~STK3 = Stack 0 ~ stack 3 buffer. P1OC = Port 1 open-drain control register. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 26... -
Page 27: Bit Definition Of System Register
S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 STK1L 0FDH S1PC12 S1PC11 S1PC10 S1PC9 S1PC8 STK1H 0FEH S0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0PC0 STK0L 0FFH S0PC12 S0PC11 S0PC10 S0PC9 S0PC8 STK0H Version 1.7 SONiX TECHNOLOGY CO., LTD Page 27... - Page 28 3. One-bit name had been declared in SN8ASM assembler with “F” prefix code. 4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers. 5. For detail description, please refer to the “System Register Quick Reference Table” Version 1.7 SONiX TECHNOLOGY CO., LTD Page 28...
-
Page 29: Accumulator
“PUSH”, “POP” save and load ACC, PFLAG data into buffers. Example: Protect ACC and working registers. INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector Version 1.7 SONiX TECHNOLOGY CO., LTD Page 29... -
Page 30: Program Flag
1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero. Note: Refer to instruction set table for detailed information of C, DC and Z flags. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 30... -
Page 31: Program Counter
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. A, #12H ; To skip, if ACC = 12H. CMPRS C0STEP ; Else jump to C0STEP. … … C0STEP: Version 1.7 SONiX TECHNOLOGY CO., LTD Page 31... - Page 32 DECS BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: DECMS instruction: DECMS BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: Version 1.7 SONiX TECHNOLOGY CO., LTD Page 32...
- Page 33 ; If ACC = 0, jump to A0POINT A1POINT ; ACC = 1, jump to A1POINT A2POINT ; ACC = 2, jump to A2POINT A3POINT ; ACC = 3, jump to A3POINT … … Version 1.7 SONiX TECHNOLOGY CO., LTD Page 33...
-
Page 34: Y, Z Registers
; Clear @YZ to be zero DECMS ; Z – 1, if Z= 0, finish the routine CLR_YZ_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … Version 1.7 SONiX TECHNOLOGY CO., LTD Page 34... -
Page 35: R Registers
Bit 3 Bit 2 Bit 1 Bit 0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Read/Write After reset Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 35... -
Page 36: Addressing Mode
; To clear Y register to access RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 36... -
Page 37: Stack Operation
STKP = 5 STK5H STK5L STKP STKP STKP = 4 STK4H STK4L STKP = 3 STK3H STK3L STKP = 2 STK2H STK2L STKP = 1 STK1H STK1L STKP = 0 STK0H STK0L Version 1.7 SONiX TECHNOLOGY CO., LTD Page 37... -
Page 38: Stack Registers
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKnL SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0 Read/Write After reset STKn = STKnH , STKnL (n = 7 ~ 0) Version 1.7 SONiX TECHNOLOGY CO., LTD Page 38... -
Page 39: Stack Operation Example
STKP Register Stack Buffer Stack Level Description STKPB2 STKPB1 STKPB0 High Byte Low Byte STK7H STK7L STK6H STK6L STK5H STK5L STK4H STK4L STK3H STK3L STK2H STK2L STK1H STK1L STK0H STK0L Free Free Version 1.7 SONiX TECHNOLOGY CO., LTD Page 39... -
Page 40: Reset
NT0, NPD: Reset status flag. Condition Description Watchdog reset Watchdog timer overflow. Reserved Power on reset and LVD reset. Power voltage is lower than LVD detecting level. External reset External reset pin detect low level status. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 40... - Page 41 High Detect Watchdog Low Detect Overflow Watchdog Normal Run Watchdog Reset Watchdog Stop System Normal Run System Status System Stop Power On External Watchdog Delay Time Reset Delay Reset Delay Time Time Version 1.7 SONiX TECHNOLOGY CO., LTD Page 41...
-
Page 42: Power On Reset
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the watchdog timer function. Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 42... -
Page 43: Brown Out Reset
DC low battery condition. When turn off the AC power, the VDD drops slowly and through the dead-band for a while. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 43... -
Page 44: The System Operating Voltage Decsription
LVD detect level. The system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage. The dead-band definition is the system minimum operating voltage above the system reset voltage. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 44... -
Page 45: Brown Out Reset Improvement
Delay Time The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by each MCU. -
Page 46: External Reset
The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference. Note: The reset circuit is no any protection against unusual power or brown out reset. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 46... -
Page 47: Diode & Rc Reset Circuit
PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener specification. Select the right zener voltage to conform the application. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 47... -
Page 48: Voltage Bias Reset Circuit
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can improve all power variation. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 48... -
Page 49: System Clock
Fcpu = Flosc/4 HOSC: High_Clk code option. Fhosc: External high-speed clock (only 6MHz) / Internal high-speed RC clock (6MHz). Flosc: Internal low-speed RC clock (about 16KHz@3V, 32KHz@5V). Fosc: System clock source. Fcpu: Instruction cycle. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 49... -
Page 50: Oscm Register
Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal low-speed oscillator will be stopped. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Version 1.7 SONiX TECHNOLOGY CO., LTD Page 50... -
Page 51: System High Clock
Crystal/Ceramic devices are driven by XIN, XOUT pins. 6M option is for high speed 6MHz. In IHRC_RTC mode, XIN/XOUT is connected with 32768Hz crystal for 0.5 sec RTC. CRYSTAL 20pF 20pF Note: Connect the Crystal/Ceramic and C as near as possible to the XIN/XOUT/VSS pins of micro-controller. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 51... -
Page 52: System Low Clock
; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1 (32K, watchdog disable) bits of OSCM register. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 52... -
Page 53: System Clock Measurement
; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P0.0 ; Measure the Fcpu frequency by oscilloscope. Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC frequency. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 53... -
Page 54: System Operation Mode
P0, P1, T0 Wakeup source P0, P1, Reset Reset EHOSC: External high clock IHRC: Internal high clock (16M RC oscillator) ILRC: Internal low clock (16K RC oscillator at 3V, 32K at 5V) Version 1.7 SONiX TECHNOLOGY CO., LTD Page 54... -
Page 55: System Mode Switching Example
; Set CPUM1 = 1. Note: If T0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can wakeup the system backs to the previous operation mode. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 55... - Page 56 ; Set T0 timer wakeup function with 0.5 sec RTC. B0BSET FT0ENB ; To enable T0 timer B0BSET FT0TB ; To enable RTC function ; Go into green mode B0BCLR FCPUM0 ;To set CPUMx = 10 B0BSET FCPUM1 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 56...
-
Page 57: Wakeup
The wakeup time is as the following. The wakeup time = 1/Fosc * 2048 = 0.341 ms (Fosc = 6MHz) The total wakeup time = 0.341 ms + oscillator start-up time Version 1.7 SONiX TECHNOLOGY CO., LTD Page 57... -
Page 58: Interrupt
Global Interrupt Request Signal TC0IRQ TC0 Time Out 2-Bit Enable USBIRQ USB Process End Latchs Gating T1IRQ T1 Trigger T2IRQ T2 Trigger Note: The GIE bit must enable during all interrupt operation. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 58... -
Page 59: Inten Interrupt Enable Register
TC0IEN: TC0 timer interrupt control bit. 0 = Disable TC0 interrupt function. 1 = Enable TC0 interrupt function. Bit 6 USBIEN: USB interrupt control bit. 0 = Disable USB interrupt function. 1 = Enable USB interrupt function. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 59... -
Page 60: Intrq Interrupt Request Register
0 = Disable global interrupt. 1 = Enable global interrupt. Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE Note: The GIE bit must enable during all interrupt operation. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 60... -
Page 61: Push, Pop Routine
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine executed. START INT_SERVICE START: … INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector … ENDP Version 1.7 SONiX TECHNOLOGY CO., LTD Page 61... -
Page 62: Int0 (P0.0) Interrupt Operation
A, #18H B0MOV PEDGE, A ; Set INT0 interrupt trigger as bi-direction edge. B0BSET FP00IEN ; Enable INT0 interrupt service B0BCLR FP00IRQ ; Clear INT0 interrupt request flag B0BSET FGIE ; Enable GIE Version 1.7 SONiX TECHNOLOGY CO., LTD Page 62... - Page 63 ; P00IRQ = 0, exit interrupt vector B0BCLR FP00IRQ ; Reset P00IRQ … ; INT0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.7 SONiX TECHNOLOGY CO., LTD Page 63...
-
Page 64: T0 Interrupt Operation
A, #74H B0MOV T0C, A ; Reset T0C. … ; T0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.7 SONiX TECHNOLOGY CO., LTD Page 64... -
Page 65: Tc0 Interrupt Operation
A, #74H B0MOV TC0C, A ; Reset TC0C. … ; TC0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.7 SONiX TECHNOLOGY CO., LTD Page 65... -
Page 66: Usb Interrupt Operation
; USBIRQ = 0, exit interrupt vector B0BCLR FUSBIRQ ; Reset USBIRQ … ; USB interrupt service routine … EXIT_INT: ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.7 SONiX TECHNOLOGY CO., LTD Page 66... -
Page 67: T1 Interrupt Operation
A, T1C B0MOV T1CBUF, A ; Save pulse width. … ; T1 interrupt service routine … EXIT_INT: ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.7 SONiX TECHNOLOGY CO., LTD Page 67... -
Page 68: T2 Interrupt Operation
A, T2C B0MOV T2CBUF, A ; Save pulse width. … ; T2 interrupt service routine … EXIT_INT: ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.7 SONiX TECHNOLOGY CO., LTD Page 68... -
Page 69: Multi-Interrupt Operation
; Jump to exit of IRQ B0BTS0 FT2IRQ ; Check T2IRQ INTT2 ; Jump to T2 interrupt service routine INT_EXIT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.7 SONiX TECHNOLOGY CO., LTD Page 69... -
Page 70: O Port
; Set all ports to be output mode. B0MOV P0M, A B0MOV P1M, A B0MOV P5M, A B0BCLR P1M.2 ; Set P1.2 to be input mode. B0BSET P1M.2 ; Set P1.2 to be output mode. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 70... -
Page 71: I/O Pull Up Register
Note: P03~P06 are input I/O with pull up resistor, so there has no P03R~P06R pull up resistor control bit. Example: I/O Pull up Register A, #0FFH ; Enable Port0, 1, 5 Pull-up register, B0MOV P0UR, A B0MOV P1UR, A B0MOV P5UR, A Version 1.7 SONiX TECHNOLOGY CO., LTD Page 71... -
Page 72: I/O Open-Drain Register
Example: Disable P1.0 to open-drain mode and output low. A, #0 ; Disable P1.0 open-drain function. B0MOV P1OC, A Note: After disable P1.0 open-drain function, P1.0 mode returns to last I/O mode. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 72... -
Page 73: I/O Port Data Register
Example: Write one bit data to output port. B0BSET P1.3 ; Set P1.3 and P5.5 to be “1”. B0BSET P5.5 B0BCLR P1.3 ; Set P1.3 and P5.5 to be “0”. B0BCLR P5.5 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 73... -
Page 74: Timers
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the main routine of the program. Main: A,#5AH ; Clear the watchdog timer. B0MOV WDTR,A … CALL SUB1 CALL SUB2 … … … MAIN Version 1.7 SONiX TECHNOLOGY CO., LTD Page 74... - Page 75 ; I/O and RAM are correct. Clear watchdog timer and ; execute program. B0BSET FWDRST ; Only one clearing watchdog timer of whole program. … CALL SUB1 CALL SUB2 … … … MAIN Version 1.7 SONiX TECHNOLOGY CO., LTD Page 75...
-
Page 76: Timer 0 (T0)
Load T0TB Fcpu T0C 8-Bit Binary Up Counting Counter CPUM0,1 T0 Time Out T0ENB Note: In RTC mode, the T0 interval time is fixed at 0.5 sec and T0C is 256 counts. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 76... -
Page 77: T0M Mode Register
T0ENB: T0 counter control bit. 0 = Disable T0 timer. 1 = Enable T0 timer. Note: T0RATE is not available in RTC mode. The T0 interval time is fixed at 0.5 sec. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 77... -
Page 78: T0C Counting Register
1.33 us Fcpu/4 0.171 ms 0.67 us Fcpu/2 0.085 ms 0.33 us Note: In RTC mode, T0C is 256 counts and generatesT0 0.5 sec interval time. Don’t change T0C value in RTC mode. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 78... -
Page 79: T0 Timer Operation Sequence
Set T0 interrupt interval time. A,#7FH B0MOV T0C,A ; Set T0C value. Set T0 timer function mode. B0BSET FT0IEN ; Enable T0 interrupt function. Enable T0 timer. B0BSET FT0ENB ; Enable T0 timer. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 79... -
Page 80: Timer/Counter 0 (Tc0)
TC0 / 2 P5.4 TC0R Reload ALOAD0, TC0OUT Data Buffer TC0 Rate (Fcpu/2~Fcpu/256) PWM0OUT Compare TC0CKS TC0ENB Fcpu Load TC0C 8-Bit Binary Up TC0 Time Out Counting Counter INT0 (Schmitter Trigger) CPUM0,1 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 80... -
Page 81: Tc0M Mode Register
0 = Disable TC0 timer. 1 = Enable TC0 timer. Note: When TC0CKS=1, TC0 became an external event counter and TC0RATE is useless. No more P0.0 interrupt request will be raised. (P0.0IRQ will be always 0). Version 1.7 SONiX TECHNOLOGY CO., LTD Page 81... -
Page 82: Tc0C Counting Register
21.33 us Fcpu/64 2.731 ms 10.67 us Fcpu/32 1.365 ms 5.33 us Fcpu/16 0.683 ms 2.67 us Fcpu/8 0.341 ms 1.33 us Fcpu/4 0.171 ms 0.67 us Fcpu/2 0.085 ms 0.33 us Version 1.7 SONiX TECHNOLOGY CO., LTD Page 82... -
Page 83: Tc0R Auto-Load Register
TC0R initial value = N - (TC0 interrupt interval time * input clock) = 256 - (1ms * 6MHz / 1 / 64) = 256 - (10 * 6 * 10 / 1 / 64) = 162 = A2H Version 1.7 SONiX TECHNOLOGY CO., LTD Page 83... -
Page 84: Tc0 Clock Frequency Output (Buzzer)
; Enable TC0 output to P5.4 and disable P5.4 I/O function B0BSET FALOAD1 ; Enable TC0 auto-reload function B0BSET FTC0ENB ; Enable TC0 timer Note: Buzzer output is enable, and “PWM0OUT” must be “0”. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 84... -
Page 85: Tc0 Timer Operation Sequence
Set TC0 timer function mode. B0BSET FTC0IEN ; Enable TC0 interrupt function. B0BSET FTC0OUT ; Enable TC0OUT (Buzzer) function. B0BSET FPWM0OUT ; Enable PWM function. Enable TC0 timer. B0BSET FTC0ENB ; Enable TC0 timer. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 85... -
Page 86: Pwm0 Mode
187.5K Overflow per 16 count The Output duty of PWM is with different TC0R. Duty range is from 0/256~255/256. …… …… …… …… TC0 Clock TC0R=00H High TC0R=01H High TC0R=80H High TC0R=FFH Version 1.7 SONiX TECHNOLOGY CO., LTD Page 86... -
Page 87: Tcxirq And Pwm Duty
PWM0 Output (Duty Range 0~63) TC0 Overflow, TC0IRQ = 1 0xFF TC0C Value 0x00 PWM0 Output (Duty Range 0~31) TC0 Overflow, TC0IRQ = 1 0xFF TC0C Value 0x00 PWM0 Output (Duty Range 0~15) Version 1.7 SONiX TECHNOLOGY CO., LTD Page 87... -
Page 88: Pwm Duty With Tcxr Changing
2 and period 4, and the new duty is changed in next period. By the way, system can avoid the PWM not changing or H/L changing twice in the same cycle and will prevent the unexpected or error operation. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 88... -
Page 89: Pwm Program Example
TC0R, A INCMS BUF0 ; Get the new TC0R value from the BUF0 buffer defined by ; programming. B0MOV A, BUF0 B0MOV TC0R, A Note: The PWM can work with interrupt request. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 89... -
Page 90: T1, T2 8-Bit Timer Capture
TnIRQ=1, TnC Stops Counting. TnIRQ Cleared by Firmware TnENB Tn Rate (Fcpu/2~Fcpu/256) Fcpu 8-Bit Binary Up TnIRQ = 1 Counting Counter CPUM0,1 TnC Counts TnC Stops TnG1,0 Trigger Trigger External Input Signal Trigger Edge Selection Version 1.7 SONiX TECHNOLOGY CO., LTD Page 90... -
Page 91: Tnm Mode Register
T1C0 Read/Write After reset 0AEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T2C7 T2C6 T2C5 T2C4 T2C3 T2C2 T2C1 T2C0 Read/Write After reset Version 1.7 SONiX TECHNOLOGY CO., LTD Page 91... -
Page 92: Tn Timer Capture Operation
Fcpu/16 0.683 ms 2.67 us 2.67us~0.683 ms 374.53KHz~1.46KHz Fcpu/8 0.341 ms 1.33 us 1.33us~0.341 ms 751.88KHz~2.94KHz Fcpu/4 0.171 ms 0.67 us 0.67us~0.171 ms 1.49MHz~5.85KHz Fcpu/2 0.085 ms 0.33 us 0.33us~0.085 ms 3.03MHz~11.76KHz Version 1.7 SONiX TECHNOLOGY CO., LTD Page 92... -
Page 93: Tn Input Period Measurement
Tn Input Signal Tn Timer Counter Rising edge trigger period measurement waveform. Rising edge trigger. Rising edge trigger. Tn start to count. Tn stop counting. TnIRQ=0 TnIRQ=1. Tn Input Signal Tn Timer Counter Version 1.7 SONiX TECHNOLOGY CO., LTD Page 93... - Page 94 T1CBUF, A ; Save T1C. … ; Application program. ; Clear T1C. B0BCLR FT1IRQ ; Clear T1IRQ for next frequency measurement. … ; Reload ACC and PFLAG. RETI ; Exit interrupt service routine. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 94...
-
Page 95: Tn Input Pulse Width Measurement
Tn Input Signal Tn Timer Counter Negative pulse width measurement waveform. Falling edge trigger. Rising edge trigger. Tn start to count. Tn stop counting. TnIRQ=0 TnIRQ=1. Tn Input Signal Tn Timer Counter Version 1.7 SONiX TECHNOLOGY CO., LTD Page 95... - Page 96 T1CBUF, A ; Save T1C. … ; Application program. ; Clear T1C. B0BCLR FT1IRQ ; Clear T1IRQ for next frequency measurement. … ; Reload ACC and PFLAG. RETI ; Exit interrupt service routine. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 96...
-
Page 97: Universal Serial Bus (Usb)
The USB is the answer to connectivity for the PC architecture. A fast, bi-directional, isochronous, low-cost, dynamically attachable serial interface is consistent with the requirements of the PC platform of today and tomorrow. The SONIX USB microcontrollers are optimized for human-interface computer peripherals such as a mouse, joystick, and game pad. -
Page 98: Usb Interrupt
EP0_In ; Jump to EP0 In Token routine. b0bts0 UE0R.6 ; check EP0_Out_Token or Setup token jmp EP0_Setup ; Jump to Setup routine. b0bclr UE0R.5 ; Clear out token flag RETI Version 1.7 SONiX TECHNOLOGY CO., LTD Page 98... -
Page 99: Usb Enumeration
After the bit is set, the D- will pull up automatically to indicate the low speed device to the USB host. 0 = Disable USB device function. 1 = Enable USB device function. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 99... -
Page 100: Usb Endpoint 0 Enable Register
1 = A valid SETUP packet has been received. Bit 7 UE0E: USB endpoint 0 function enable bit. 0 = disable USB endpoint 0 function. 1 = enable USB endpoint 0 function. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 100... -
Page 101: Usb Endpoint 1 Enable Register
;FIFO address + 1 EP1_WR_RAM_data MOUSE_X_AXIS ;Write MOUSE_X_AXIS to FIFO. … … a, #0x88 ;1.keep enable ep1 ;2.counter = 8 (Send 8 byte) ;3.Ready to transfer (bit4=0), ACK handshake B0MOV UE1R, a Version 1.7 SONiX TECHNOLOGY CO., LTD Page 101... -
Page 102: Example: Check The Endpoint 1'S Out Request
UE2DI=1, endpoint IN data FIFO 1 FIFO 0 FIFO 0 FIFO 1 Bit 7 UE2E: USB endpoint 2 function enable bit. 0 = disable USB endpoint 2 function. 1 = enable USB endpoint 2 function. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 102... -
Page 103: Usb Endpoint 3 Enable Register
Address [1F]~address [18]: data buffer for endpoint 3. Check the bit 6 of the UE3E register (0xA4H) to select the right FIFO. The following examples show how to do select the right FIFO address pointer. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 103... - Page 104 UDP1, A user_define_routine Example 4. Write data to EP2 FIFO. EP2_FIFO_WRITE_data: B0BTS1 0xA3.6 ;check the bit to select the right FIFO write_endpoint2_FIFO_UDR0 write_endpoint2_FIFO_UDR1 write _endpoint2_FIFO_UDR0 A, UDR0 user_define_routine write _endpoint2_FIFO_UDR1 A, UDR1 user_define_routine Version 1.7 SONiX TECHNOLOGY CO., LTD Page 104...
-
Page 105: Usb Data Register
1 = Set to 1 by hardware when USB suspend request. Bit 7 FFS0: endpoint 0 FIFO selection control bit. FFS0 UE0DO=1, endpoint OUT data UE0DI=1, endpoint IN data FIFO 1 FIFO 0 FIFO 0 FIFO 1 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 105... -
Page 106: Upid Register
1 = set this bit and the bit 4 of UE3R register will send the STALL handshake response to any IN token sent to endpoint 3. 0 = Disable endpoint 3 STALL handshake response. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 106... -
Page 107: Ps/2 Interface
Firmware must include clock 15KHz signal generator, odd parity calculate, start/stop/ack bit routine to get a basic PS/2 protocol signal, and follow PS/2 protocol specification to define PC’s peripheral device (mouse or keyboard) transmitting data form and contents. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 107... -
Page 108: Ps2_1 Descripiton
1 = Data 1. Bit [1:0] SDAM, SCKM: SDA, SCK mode control bit. 0 = Input mode. 1 = Output mode. Note: Use PS2_1 for PS/2 communication, the USB must be disable (UDE=0). Version 1.7 SONiX TECHNOLOGY CO., LTD Page 108... -
Page 109: Ps2_2 Descripiton
P1.0, P1.1 must be set as open-drain mode. Use firmware to make PS/2 communication routine. VDD (5V) P10M P10OC=1 P1.0 P1.0 Output VDD (5V) HOST Latch Terminal P11M P11OC=1 P1.1 P1.1 Output Latch Version 1.7 SONiX TECHNOLOGY CO., LTD Page 109... -
Page 110: Instruction Table
Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1. 2. If branch condition is true then “S = 1”, otherwise “S = 0”. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 110... -
Page 111: Development Tool
USB 1.1 Low-Speed 8-Bit Micro-Controller DEVELOPMENT TOOL SONIX provides ICE (in circuit emulation), IDE (Integrated Development Environment), EV-kit and firmware library for USB application development. ICE and EV-kit are external hardware device and IDE is a friendly user interface for firmware development and emulation. - Page 112 13 12 10 9 Link Pin 2 & Pin 13 Link Pin 3 & Pin 5 Link Pin 6 & Pin 9 Link Pin 10 & Pin 12 2 3 5 6 6MHz Crystal 6MHz Version 1.7 SONiX TECHNOLOGY CO., LTD Page 112...
-
Page 113: Sn8P2200 Ev-Kit
U6: USB and PS/2 pull-up resistors control device. JP4: PS2_1 connector. JP10: PS2_2 connector. JP11: GPIO connector. U7~U10: SN8P2204, SN8P2203, SN8P2202, SN8P2201 DIP form connector for connecting to user’s target board. S1: PS2_2 (from P1.0, P1.1) pull-up resistor. Version 1.7 SONiX TECHNOLOGY CO., LTD... - Page 114 SCLK_D+ The SN8P2204 EV-kit USB PHY can be U4 “TRXU11” or U5 “SN8P2201S”. The PHY IC is offered by Sonix. Using TRXU11, U2 pin17, 20, 21 must be cut off, or the USB emulation can’t be successful. Using SN8P2201S PHY, the EV-kit needn’t modify any parts.
-
Page 115: Ice And Ev-Kit Application Notic
Using ICE and EV-kit to emulate SN8P2200 operation, the “ICE_MODE” should be declared in head of program to make sure ICE+EV-kit operating correctly. ICE_MODE equ 0 ; Compile for real chip. ICE_MODE equ 1 ; ICE+EV-kit emulation. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 115... -
Page 116: Ide (Integrated Development Environment)
12.4 IDE (Integrated Development Environment) The IDE for SN8P2200 development and emulation is base on Sonix M2IDE to add USB FiFo window. The user interface and operation method is equal to M2IDE. Please refer to M2IDE document about basic operation. -
Page 117: Electrical Characteristic
Vdd= 3V, 4Mhz 0.25 Idd4 Fcpu = Fosc/4 Vdd=5V, ILRC 32Khz Watchdog Disable) Vdd=3V, ILRC 16Khz LVD Voltage Vdet0 Low voltage reset level. * These parameters are for design reference, not tested. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 117... -
Page 118: Otp Programming Pin
DIP38 DIP12 DIP38 DIP13 DIP36 DIP14 DIP35 DIP15 DIP34 DIP16 DIP33 DIP17 DIP32 DIP18 DIP31 DIP19 DIP30 DIP20 DIP29 DIP21 DIP28 DIP22 DIP27 DIP23 DIP26 DIP24 DIP25 JP3 for MP transition board Version 1.7 SONiX TECHNOLOGY CO., LTD Page 118... -
Page 119: Programming Pin Mapping
EZ Writer / MP Writer OTP IC / JP3 Pin Assigment Connector Number Name Number Number Number Number P5.0 P5.0 P5.0 P5.0 P1.0 P1.0 P1.0 P1.0 P5.1 P5.1 P5.1 P5.1 ALSB/PDB P1.1 P1.1 P1.1 P1.1 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 119... -
Page 120: Package Information
1.400 35.306 35.306 35.560 0.310 7.874 0.283 0.288 0.293 7.188 7.315 7.442 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.330 0.350 0.370 8.382 8.890 9.398 θ° 0° 7° 15° 0° 7° 15° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 120... -
Page 121: Sk-Dip 24 Pin
31.242 31.75 32.51 0.300 BSC 7.62 BSC 0.252 0.258 0.263 6.553 5.994 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.335 0.355 0.375 8.509 9.017 9,525 θ° 0° 7° 15° 0° 7° 15° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 121... -
Page 122: P-Dip 18 Pin
0.920 22.352 22.860 23.368 0.300 7.620 0.245 0.250 0.255 6.223 6.350 6.477 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.335 0.355 0.375 8.509 9.017 9.525 θ° 0° 7° 15° 0° 7° 15° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 122... -
Page 123: P-Dip 14 Pin
0.775 18.669 1.905 19.685 0.300 7.62 0.245 0.250 0.255 6.223 6.35 6.477 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.335 0.355 0.375 8.509 9.017 9.525 θ° 0° 7° 15° 0° 7° 15° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 123... -
Page 124: Sop 28 Pin
0.305 0.697 0.705 0.713 17.704 17.907 18.110 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.325 10.643 0.016 0.033 0.050 0.406 0.838 1.270 θ° 0° 4° 8° 0° 4° 8° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 124... -
Page 125: Sop 24 Pin
0.102 0.599 0.600 0.624 15.214 15.24 15.84 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.337 10.643 0.016 0.035 0.050 0.406 0.889 1.270 θ° 0° 4° 8° 0° 4° 8° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 125... -
Page 126: Sop 20 Pin
0.305 0.496 0.502 0.508 12.598 12.751 12.903 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.325 10.643 0.016 0.033 0.050 0.406 0.838 1.270 θ° 0° 4° 8° 0° 4° 8° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 126... -
Page 127: Sop 18 Pin
0.305 0.447 0.455 0.463 11.354 11.557 11.760 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.325 10.643 0.016 0.033 0.050 0.406 0.838 1.270 θ° 0° 4° 8° 0° 4° 8° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 127... -
Page 128: Sop 14 Pin
0.2490 0.336 0.341 0.344 8.5344 8.6614 8.7376 0.150 0.154 0.157 3.81 3.9116 3.9878 0.050 1.27 0.228 0.236 0.244 5.7912 5.9944 6.1976 0.015 0.025 0.050 0.381 0.635 1.27 θ° 0° 8° 0° 8° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 128... -
Page 129: Ssop 28 Pin
0.39 0.40 0.41 7.40 7.80 8.20 0.29 0.31 0.32 5.00 5.30 5.60 0.20 0.21 0.22 0.0259BSC 0.65BSC 0.63 0.90 1.03 0.02 0.04 0.04 0.09 0.00 θ° 0° 4° 8° 0° 4° 8° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 129... -
Page 130: Ssop 24 Pin
3.911 3.987 0.150 0.154 0.157 0.203 0.304 0.008 0.012 0.177 0.254 0.007 0.010 0.025 BASIC 0.635 BASIC 0.406 0.635 1.27 0.016 0.025 0.050 1.041 BASIC 0.041 BASIC θ° 0° 8° 0° 8° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 130... -
Page 131: Ssop 20 Pin
3.800 3.900 4.000 0.025 0.635 0.010 0.017 0.020 0.250 0.420 0.500 0.016 0.025 0.050 0.400 0.635 1.270 0.039 0.041 0.043 1.000 1.050 1.100 0.059 1.500 0.004 0.100 θ° 0° 8° 0° 8° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 131... -
Page 132: Ssop 16 Pin
0.010 0.1778 0.254 0.007 0.009 0.1778 0.2286 0.189 0.197 4.8006 5.0038 0.150 0.157 3.81 3.9878 0.228 0.244 5.7912 6.1976 0.016 0.050 0.4064 1.27 0.025 BASIC 0.635 BASIC θ° 0° 8° 0° 8° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 132... -
Page 133: Qfn 16 Pin
SN8P2200 Series USB 1.1 Low-Speed 8-Bit Micro-Controller 15.14 QFN 16 PIN Version 1.7 SONiX TECHNOLOGY CO., LTD Page 133... -
Page 134: Marking Definition
Marking Definition 16.1 INTRODUCTION There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit MCU for order or obtain information. This definition is only for Blank OTP MCU. 16.2 MARKING INDETIFICATION SYSTEM SN8 X Part No. -
Page 135: Marking Example
..9=09 A=10 B=11 ..1=January Month 2=February ..9=September A=October B=November C=December 03= 2003 Year 04= 2004 05= 2005 06= 2006 ..Version 1.7 SONiX TECHNOLOGY CO., LTD Page 135... - Page 136 SONIX product could create a situation where personal injury or death may occur.
Need help?
Do you have a question about the SN8P2203 and is the answer not in the manual?
Questions and answers