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SN8P2624
USER'S MANUAL
Preliminary Specification Version 0.3
SN8P2624
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
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8-Bit Micro-Controller
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Version 0.3
SN8P2624
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Summary of Contents for SONIX SN8P2624
- Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.
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Page 2: Amendent History
Nov 2005 Modify Topr value. Dec 2005 Modify Brown-Out Reset description Remove power consumption(Pc) Remove Noise Filter Enable Working Voltage Remove High clock32K mode Add Fcpu limitation by noise filter. Modify ELECTRICAL CHARACTERISTIC. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 2... -
Page 3: Table Of Contents
IMMEDIATE ADDRESSING MODE..................33 2.2.2 DIRECTLY ADDRESSING MODE ..................33 2.2.3 INDIRECTLY ADDRESSING MODE ..................33 STACK OPERATION........................34 2.3.1 OVERVIEW ..........................34 2.3.2 STACK REGISTERS ......................... 35 2.3.3 STACK OPERATION EXAMPLE..................... 36 Version 0.3 SONiX TECHNOLOGY CO., LTD Page 3... - Page 4 WAKEUP ............................56 5.3.1 OVERVIEW ..........................56 5.3.2 WAKEUP TIME........................56 5.3.3 P1W WAKEUP CONTROL REGISTER ................... 57 INTERRUPT............................58 OVERVIEW............................. 58 INTEN INTERRUPT ENABLE REGISTER................... 59 INTRQ INTERRUPT REQUEST REGISTER ................60 Version 0.3 SONiX TECHNOLOGY CO., LTD Page 4...
- Page 5 PWM PROGRAM EXAMPLE ....................85 INSTRUCTION TABLE ........................86 ELECTRICAL CHARACTERISTIC ....................87 10.1 ABSOLUTE MAXIMUM RATING ....................87 10.2 ELECTRICAL CHARACTERISTIC....................87 10.3 CHARACTERISTIC GRAPHS ....................... 88 OTP PROGRAMMING PIN......................89 Version 0.3 SONiX TECHNOLOGY CO., LTD Page 5...
- Page 6 WRITER V2.5 AND V3.0 TRANSITION BOARD SOCKET PIN ASSIGNMENT ....89 11.1.3 PROGRAMMING PIN MAPPING ................... 90 PACKAGE INFORMATION ......................91 12.1 SK-DIP 28 PIN ..........................91 12.2 SOP 28 PIN............................92 12.3 SSOP 28 PIN............................. 93 Version 0.3 SONiX TECHNOLOGY CO., LTD Page 6...
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Page 7: Product Overview
All ROM area lookup table function (MOVC) Features Selection Table Timer Green Wakeup CHIP ROM RAM Stack Package Mode Buzzer Pin No. SN8P1604A 4K*16 128 SK-DIP28/SOP28 SN8P2604 4K*16 128 SK-DIP28/SOP28/SSOP28 SN8P26042 4K*16 128 P-DIP20/SOP20/SSOP20 SN8P2624 2K*16 SK-DIP28/SOP28/SSOP28 Version 0.3 SONiX TECHNOLOGY CO., LTD Page 7... -
Page 8: System Block Diagram
8-Bit Micro-Controller 1.2 SYSTEM BLOCK DIAGRAM EXTERNAL INTERNAL (Low Voltage Detector) HIGH OSC. LOW RC FLAGS WATCHDOG TIMER TIMING GENERATOR PWM 1 PWM1 BUZZER 1 BUZZER1 SYSTEM REGISTERS INTERRUPT CONTROL TIMER & COUNTER Version 0.3 SONiX TECHNOLOGY CO., LTD Page 8... -
Page 9: Pin Assignment
SN8P2624X (SSOP 28 pins) P0.1/INT1 RST/VPP/P0.2 P5.4 XOUT/Fcpu P2.7 P0.0/INT0 P2.6 P5.0 P2.5 P5.1 P2.4 P5.2 P2.3 P5.3/BZ1/PWM1 P2.2 P1.0 P2.1 P1.1 P2.0 P1.2 P1.7 P1.3 P1.6 P1.4 P1.5 SN8P2624K SN8P2624S SN8P2624X Version 0.3 SONiX TECHNOLOGY CO., LTD Page 9... -
Page 10: Pin Descriptions
Port 5 bi-direction pin. Schmitt trigger structure as input mode. P5.0~P5.2, P5.4 Built-in pull-up resisters. Port 5.3 bi-direction pin. Schmitt trigger structure as input mode. P5.3/BZ1/PWM1 Built-in pull-up resisters. TC1 ÷ 2 signal output pin for buzzer or PWM1 output pin. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 10... -
Page 11: Pin Circuit Diagrams
Input Bus Output Output Bus Latch Port 1.0, P1.1 structure: Pull-Up PnM, PnUR Input Bus Output Output Bus Latch Open-Drain P1OC Port 0.2 structure: Ext. Reset Code Option Int. Bus Int. Rst Version 0.3 SONiX TECHNOLOGY CO., LTD Page 11... -
Page 12: Central Processor Unit (Cpu)
Jump to user start address General purpose area 0007H 0008H Interrupt vector User interrupt vector 0009H User program 000FH 0010H 0011H General purpose area 03FCH End of user program 03FDH Reserved 03FEH 03FFH Version 0.3 SONiX TECHNOLOGY CO., LTD Page 12... -
Page 13: Reset Vector (0000H)
Example: Defining Reset Vector ; 0000H START ; Jump to user program address. … ; 0010H, The head of user program. START: … ; User program … ENDP ; End of program Version 0.3 SONiX TECHNOLOGY CO., LTD Page 13... -
Page 14: Interrupt Vector (0008H)
; End of interrupt service routine RETI … START: ; The head of user program. … ; User program … START ; End of user program … ENDP ; End of program Version 0.3 SONiX TECHNOLOGY CO., LTD Page 14... - Page 15 ENDP ; End of program. Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
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Page 16: Look-Up Table Description
Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Example: INC_YZ macro. INC_YZ MACRO INCMS ; Z+1 ; Not overflow INCMS ; Y+1 ; Not overflow ENDM Version 0.3 SONiX TECHNOLOGY CO., LTD Page 16... - Page 17 ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 … TABLE1: 0035H ; To define a word (16 bits) data. 5105H 2012H … Version 0.3 SONiX TECHNOLOGY CO., LTD Page 17...
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Page 18: Jump Table Description
; ACC = 3, jump to A3POINT SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size. - Page 19 SN8P2624 8-Bit Micro-Controller Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”. B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A ; The number of the jump table listing is five. A0POINT ; ACC = 0, jump to A0POINT A1POINT ;...
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Page 20: Checksum Calculation
; If Not jump to checksum calculate CHECKSUM_END ; If Yes checksum calculated is done. Y_ADD_1: INCMS ; Increase Y ; Jump to checksum calculate CHECKSUM_END: … … END_USER_CODE: ; Label of program end Version 0.3 SONiX TECHNOLOGY CO., LTD Page 20... -
Page 21: Code Option Table
If users define watchdog as “Always_On”, assembler will Enable “Watch_Dog” automatically. Fcpu code option is only available for High Clock. Fcpu of slow mode is Fosc/4 (the Fosc is internal low clock). Version 0.3 SONiX TECHNOLOGY CO., LTD Page 21... -
Page 22: Data Memory (Ram)
General purpose area “ “ “ 03Fh BANK 0 080h 080h~0FFh of Bank 0 store system registers (128 bytes). “ “ System register “ “ “ 0FFh End of bank 0 area Version 0.3 SONiX TECHNOLOGY CO., LTD Page 22... -
Page 23: System Register
WDTR = Watchdog timer clear register. STKP = Stack pointer buffer. STK0~STK7 = Stack 0 ~ stack 7 buffer. @YZ = RAM YZ indirect addressing index pointer. @HL = RAM HL indirect addressing index pointer. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 23... -
Page 24: Bit Definition Of System Register
2. All of register names had been declared in SN8ASM assembler. 3. One-bit name had been declared in SN8ASM assembler with “F” prefix code. 4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 24... -
Page 25: Accumulator
“PUSH”, “POP” save and load ACC, PFLAG data into buffers. Example: Protect ACC and working registers. INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector Version 0.3 SONiX TECHNOLOGY CO., LTD Page 25... -
Page 26: Program Flag
1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero. Note: Refer to instruction set table for detailed information of C, DC and Z flags. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 26... -
Page 27: Program Counter
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. A, #12H ; To skip, if ACC = 12H. CMPRS C0STEP ; Else jump to C0STEP. … … C0STEP: Version 0.3 SONiX TECHNOLOGY CO., LTD Page 27... - Page 28 BUF0 DECS C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: DECMS instruction: BUF0 DECMS C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: Version 0.3 SONiX TECHNOLOGY CO., LTD Page 28...
- Page 29 ; If ACC = 0, jump to A0POINT A1POINT ; ACC = 1, jump to A1POINT A2POINT ; ACC = 2, jump to A2POINT A3POINT ; ACC = 3, jump to A3POINT … … Version 0.3 SONiX TECHNOLOGY CO., LTD Page 29...
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Page 30: H, L Registers
; Clear @HL to be zero DECMS ; L – 1, if L = 0, finish the routine CLR_HL_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … … Version 0.3 SONiX TECHNOLOGY CO., LTD Page 30... -
Page 31: Y, Z Registers
; Clear @YZ to be zero DECMS ; Z – 1, if Z= 0, finish the routine CLR_YZ_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … Version 0.3 SONiX TECHNOLOGY CO., LTD Page 31... -
Page 32: R Registers
Bit 3 Bit 2 Bit 1 Bit 0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Read/Write After reset Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 32... -
Page 33: Addressing Mode
; To clear Y register to access RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 33... -
Page 34: Stack Operation
STKP = 5 STK5H STK5L STKP STKP STKP = 4 STK4H STK4L STKP = 3 STK3H STK3L STKP = 2 STK2H STK2L STKP = 1 STK1H STK1L STKP = 0 STK0H STK0L Version 0.3 SONiX TECHNOLOGY CO., LTD Page 34... -
Page 35: Stack Registers
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0 STKnL Read/Write After reset STKn = STKnH , STKnL (n = 7 ~ 0) Version 0.3 SONiX TECHNOLOGY CO., LTD Page 35... -
Page 36: Stack Operation Example
STKP Register Stack Buffer Stack Level Description STKPB2 STKPB1 STKPB0 High Byte Low Byte STK7H STK7L STK6H STK6L STK5H STK5L STK4H STK4L STK3H STK3L STK2H STK2L STK1H STK1L STK0H STK0L Free Free Version 0.3 SONiX TECHNOLOGY CO., LTD Page 36... -
Page 37: Reset
High Detect Low Detect Watchdog Overflow Watchdog Normal Run Watchdog Reset Watchdog Stop System Normal Run System Status System Stop Power On External Watchdog Delay Time Reset Delay Reset Delay Time Time Version 0.3 SONiX TECHNOLOGY CO., LTD Page 37... -
Page 38: Power On Reset
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the watchdog timer function. Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 38... -
Page 39: Brown Out Reset
DC low battery condition. When turn off the AC power, the VDD drops slowly and through the dead-band for a while. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 39... -
Page 40: The System Operating Voltage Decsription
2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips) and use external reset (“ Zener diode reset circuit”, “Voltage bias reset circuit”, “External reset IC”). The structure can improve noise effective and get good EFT characteristic. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 40... - Page 41 Delay Time The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by each MCU.
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Page 42: External Reset
The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference. Note: The reset circuit is no any protection against unusual power or brown out reset. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 42... -
Page 43: Diode & Rc Reset Circuit
PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener specification. Select the right zener voltage to conform the application. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 43... -
Page 44: Voltage Bias Reset Circuit
When power drops below the reset detect voltage, the system reset would be triggered, and then system executes reset sequence. That makes sure the system work well under unstable power situation. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 44... -
Page 45: External Reset Ic
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can improve all power variation. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 45... -
Page 46: System Clock
Fcpu = Flosc/4. SONIX provides a “Noise Filter” controlled by code option. In high noisy situation, the noise filter can isolate noise outside and protect system works well. The minimum Fcpu of high clock is limited at Fhosc/4 when noise filter enable. -
Page 47: Oscm Register
Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal low-speed oscillator will be stopped. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Version 0.3 SONiX TECHNOLOGY CO., LTD Page 47... -
Page 48: System High Clock
High_Clk code option. The start up time of crystal/ceramic and RC type oscillator is different. RC type oscillator’s start-up time is very short, but the crystal’s is longer. The oscillator start-up time decides reset time length. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 48... -
Page 49: Crystal/Ceramic
“R” value is to change frequency. 50P~100P is good value for “C”. XOUT pin is general purpose I/O pin. Note: Connect the R and C as near as possible to the VDD pin of micro-controller. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 49... -
Page 50: External Clock Signal
XIN pin. XOUT pin is general purpose I/O pin. External Clock Input XOUT Note: The GND of external oscillator circuit must be as near as possible to VSS pin of micro-controller. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 50... -
Page 51: System Low Clock
; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1 (32K, watchdog disable) bits of OSCM register. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 51... -
Page 52: System Clock Measurement
; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P0.0 ; Measure the Fcpu frequency by oscilloscope. Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC frequency. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 52... -
Page 53: System Operation Mode
All active All active All active All inactive P0, P1, T0 Wakeup source P0, P1, Reset Reset EHOSC: External high clock ILRC: Internal low clock (16K RC oscillator at 3V, 32K at 5V) Version 0.3 SONiX TECHNOLOGY CO., LTD Page 53... -
Page 54: System Mode Switching
; Set CPUM1 = 1. Note: If T0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can wakeup the system backs to the previous operation mode. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 54... - Page 55 Note: During the green mode with T0 wake-up function, the wakeup pins, reset pin and T0 can wakeup the system back to the last mode. T0 wake-up period is controlled by program and T0ENB must be set. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 55...
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Page 56: Wakeup
The wakeup time is as the following. The wakeup time = 1/Fosc * 2048 = 0.512 ms (Fosc = 4MHz) The total wakeup time = 0.512 ms + oscillator start-up time Version 0.3 SONiX TECHNOLOGY CO., LTD Page 56... -
Page 57: P1W Wakeup Control Register
Bit 0 P17W P16W P15W P14W P13W P12W P11W P10W Read/Write After reset Bit[7:0] P10W~P17W: Port 1 wakeup function control bits. 0 = Disable P1n wakeup function. 1 = Enable P1n wakeup function. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 57... -
Page 58: Interrupt
INT1 Trigger Interrupt Vector Address (0008H) 4-Bit Enable T0IRQ T0 Time Out Global Interrupt Request Signal Latchs Gating TC1IRQ TC1 Time Out Note: The GIE bit must enable during all interrupt operation. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 58... -
Page 59: Inten Interrupt Enable Register
0 = Disable T0 interrupt function. 1 = Enable T0 interrupt function. Bit 6 TC1IEN: TC1 timer interrupt control bit. 0 = Disable TC1 interrupt function. 1 = Enable TC1 interrupt function. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 59... -
Page 60: Intrq Interrupt Request Register
0 = Disable global interrupt. 1 = Enable global interrupt. Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE Note: The GIE bit must enable during all interrupt operation. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 60... -
Page 61: Push, Pop Routine
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine executed. START INT_SERVICE START: … INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector … ENDP Version 0.3 SONiX TECHNOLOGY CO., LTD Page 61... -
Page 62: Int0 (P0.0) Interrupt Operation
; P00IRQ = 0, exit interrupt vector B0BCLR FP00IRQ ; Reset P00IRQ … ; INT0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.3 SONiX TECHNOLOGY CO., LTD Page 62... -
Page 63: Int1 (P0.1) Interrupt Operation
; P01IRQ = 0, exit interrupt vector B0BCLR FP01IRQ ; Reset P01IRQ … ; INT1 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.3 SONiX TECHNOLOGY CO., LTD Page 63... -
Page 64: T0 Interrupt Operation
A, #74H B0MOV T0C, A ; Reset T0C. … ; T0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.3 SONiX TECHNOLOGY CO., LTD Page 64... -
Page 65: Tc1 Interrupt Operation
A, #74H B0MOV TC1C, A ; Reset TC1C. … ; TC1 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.3 SONiX TECHNOLOGY CO., LTD Page 65... -
Page 66: Multi-Interrupt Operation
; Jump to exit of IRQ B0BTS0 FTC1IRQ ; Check TC1IRQ INTTC1 ; Jump to TC1 interrupt service routine INT_EXIT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.3 SONiX TECHNOLOGY CO., LTD Page 66... -
Page 67: I/O Port
; Set all ports to be output mode. B0MOV P0M, A B0MOV P1M, A B0MOV P2M, A B0MOV P5M, A B0BCLR P1M.2 ; Set P1.2 to be input mode. B0BSET P1M.2 ; Set P1.2 to be output mode. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 67... -
Page 68: I/O Pull Up Register
Note: P0.2 is input only pin and without pull-up resister. The P0UR.2 keeps “1”. Example: I/O Pull up Register A, #0FFH ; Enable Port0, 1, 2, 5 Pull-up register, B0MOV P0UR, A B0MOV P1UR, A B0MOV P2UR, A B0MOV P5UR, A Version 0.3 SONiX TECHNOLOGY CO., LTD Page 68... -
Page 69: I/O Open-Drain Register
Example: Disable P1.0 to open-drain mode and output low. A, #0 ; Disable P1.0 open-drain function. B0MOV P1OC, A Note: After disable P1.0 open-drain function, P1.0 mode returns to last I/O mode. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 69... -
Page 70: I/O Port Data Register
Example: Write one bit data to output port. B0BSET P1.3 ; Set P1.3 and P5.5 to be “1”. B0BSET P5.5 B0BCLR P1.3 ; Set P1.3 and P5.5 to be “0”. B0BCLR P5.5 Version 0.3 SONiX TECHNOLOGY CO., LTD Page 70... -
Page 71: Timers
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the main routine of the program. Main: A,#5AH ; Clear the watchdog timer. B0MOV WDTR,A … CALL SUB1 CALL SUB2 … … … MAIN Version 0.3 SONiX TECHNOLOGY CO., LTD Page 71... - Page 72 ; I/O and RAM are correct. Clear watchdog timer and ; execute program. B0BSET FWDRST ; Only one clearing watchdog timer of whole program. … CALL SUB1 CALL SUB2 … … … MAIN Version 0.3 SONiX TECHNOLOGY CO., LTD Page 72...
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Page 73: Timer 0 (T0)
T0RATE[2:0]: T0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. … 110 = fcpu/4. 111 = fcpu/2. Bit 7 T0ENB: T0 counter control bit. 0 = Disable T0 timer. 1 = Enable T0 timer. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 73... -
Page 74: T0C Counting Register
16 us 500 ms 1953.125 us Fcpu/8 2.048 ms 8 us 250 ms 976.563 us Fcpu/4 1.024 ms 4 us 125 ms 488.281 us Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us Version 0.3 SONiX TECHNOLOGY CO., LTD Page 74... -
Page 75: T0 Timer Operation Sequence
Set T0 interrupt interval time. A,#7FH B0MOV T0C,A ; Set T0C value. Set T0 timer function mode. B0BSET FT0IEN ; Enable T0 interrupt function. Enable T0 timer. B0BSET FT0ENB ; Enable T0 timer. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 75... -
Page 76: Timer/Counter 0 (Tc1)
TC1 / 2 P5.3 TC1R Reload ALOAD1, TC1OUT Data Buffer TC1 Rate (Fcpu/2~Fcpu/256) PWM1OUT Compare TC1CKS TC1ENB Fcpu Load TC1C 8-Bit Binary Up TC1 Time Out Counting Counter INT1 (Schmitter Trigger) CPUM0,1 Version 0.3 SONiX TECHNOLOGY CO., LTD Page 76... -
Page 77: Tc1M Mode Register
0 = Disable TC1 timer. 1 = Enable TC1 timer. Note: When TC1CKS=1, TC1 became an external event counter and TC1RATE is useless. No more P0.1 interrupt request will be raised. (P0.1IRQ will be always 0). Version 0.3 SONiX TECHNOLOGY CO., LTD Page 77... -
Page 78: Tc1C Counting Register
16 us 500 ms 1953.125 us Fcpu/8 2.048 ms 8 us 250 ms 976.563 us Fcpu/4 1.024 ms 4 us 125 ms 488.281 us Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us Version 0.3 SONiX TECHNOLOGY CO., LTD Page 78... -
Page 79: Tc1R Auto-Load Register
TC1R initial value = N - (TC1 interrupt interval time * input clock) = 256 - (10ms * 4MHz / 4 / 64) = 256 - (10 * 4 * 10 / 4 / 64) = 100 = 64H Version 0.3 SONiX TECHNOLOGY CO., LTD Page 79... -
Page 80: Tc1 Clock Frequency Output (Buzzer)
; Enable TC1 output to P5.3 and disable P5.3 I/O function B0BSET FALOAD1 ; Enable TC1 auto-reload function B0BSET FTC1ENB ; Enable TC1 timer Note: Buzzer output is enable, and “PWM1OUT” must be “0”. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 80... -
Page 81: Tc1 Timer Operation Sequence
Set TC1 timer function mode. B0BSET FTC1IEN ; Enable TC1 interrupt function. B0BSET FTC1OUT ; Enable TC1OUT (Buzzer) function. B0BSET FPWM1OUT ; Enable PWM function. Enable TC1 timer. B0BSET FTC1ENB ; Enable TC1 timer. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 81... -
Page 82: Pwm1 Mode
125K Overflow per 16 count The Output duty of PWM is with different TC1R. Duty range is from 0/256~255/256. …… …… …… …… TC1 Clock TC1R=00H High TC1R=01H High TC1R=80H High TC1R=FFH Version 0.3 SONiX TECHNOLOGY CO., LTD Page 82... -
Page 83: Tcxirq And Pwm Duty
PWM1 Output (Duty Range 0~63) TC1 Overflow, TC1IRQ = 1 0xFF TC1C Value 0x00 PWM1 Output (Duty Range 0~31) TC1 Overflow, TC1IRQ = 1 0xFF TC1C Value 0x00 PWM1 Output (Duty Range 0~15) Version 0.3 SONiX TECHNOLOGY CO., LTD Page 83... -
Page 84: Pwm Duty With Tcxr Changing
2 and period 4, and the new duty is changed in next period. By the way, system can avoid the PWM not changing or H/L changing twice in the same cycle and will prevent the unexpected or error operation. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 84... -
Page 85: Pwm Program Example
TC1R, A INCMS BUF0 ; Get the new TC1R value from the BUF0 buffer defined by ; programming. B0MOV A, BUF0 B0MOV TC1R, A Note: The PWM can work with interrupt request. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 85... -
Page 86: Instruction Table
Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1. 2. If branch condition is true then “S = 1”, otherwise “S = 0”. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 86... -
Page 87: Electrical Characteristic
(No loading, Vdd= 3V, 4Mhz 0.25 Idd4 Fcpu = Fosc/4 Vdd=5V, ILRC 32Khz Watchdog Disable) Vdd=3V, ILRC 16Khz LVD detect level Low voltage detect level *These parameters are for design reference, not tested. Version 0.3 SONiX TECHNOLOGY CO., LTD Page 87... -
Page 88: Characteristic Graphs
This is for information only and devices are guaranteed to operate properly only within the specified range. SN8P2624 Wo rk ing area Fcp u 12 M 1 6M Working Voltage vs. Frequency (Noise Filter Disable、25℃) Version 0.3 SONiX TECHNOLOGY CO., LTD Page 88... -
Page 89: Otp Programming Pin
18 HLS Writer V2.5 JP1 Pin Assignment Writer V3.0 JP1 Pin Assignment Note: For supporting the body programming, SONIX writer V2.5 must update V3.0 firmware and modify circuit. Please contact SONIX agent about SONIX Writer V2.5 upgrade. Version 0.3 SONiX TECHNOLOGY CO., LTD... -
Page 90: Programming Pin Mapping
Programming Information of SN8P2600A Series Chip Name SN8P2624 EZ Writer / Writer Writer V2.5 V3.0 OTP IC / JP3 Pin Assigment Connector Connector Number Name Number Name Number Number P5.0 P1.0 P5.1 ALSB/PDB P1.1 Version 0.3 SONiX TECHNOLOGY CO., LTD Page 90... -
Page 91: Package Information
1.400 35.306 35.306 35.560 0.310 7.874 0.283 0.288 0.293 7.188 7.315 7.442 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.330 0.350 0.370 8.382 8.890 9.398 θ° 0° 7° 15° 0° 7° 15° Version 0.3 SONiX TECHNOLOGY CO., LTD Page 91... -
Page 92: Sop 28 Pin
0.305 0.697 0.705 0.713 17.704 17.907 18.110 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.325 10.643 0.016 0.033 0.050 0.406 0.838 1.270 θ° 0° 4° 8° 0° 4° 8° Version 0.3 SONiX TECHNOLOGY CO., LTD Page 92... -
Page 93: Ssop 28 Pin
0.39 0.40 0.41 7.40 7.80 8.20 0.29 0.31 0.32 5.00 5.30 5.60 0.20 0.21 0.22 0.0259BSC 0.65BSC 0.63 0.90 1.03 0.02 0.04 0.04 0.09 0.00 θ° 0° 4° 8° 0° 4° 8° Version 0.3 SONiX TECHNOLOGY CO., LTD Page 93... - Page 94 SONIX product could create a situation where personal injury or death may occur.
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