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SN8P2318 Series
USER'S MANUAL
Version 1.5
SN8P2317
SN8P2318
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
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Page 1
SN8P2318 Series
C-type LCD, RFC 8-Bit Micro-Controller
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Version 1.5
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Summary of Contents for SONIX SN8P2308
- Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.
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Page 2: Amendent History
Modify “ELECTRICAL CHARACTERICS” chapter operating temperature from 0~70℃ to VER 1.4 Sep. 2012 -20~85℃ and others. VER 1.5 Jun. 2013 1. Modify PROGRAMMING PIN MAPPING content. 2. VLCD and VDD pin have to short together. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 2... -
Page 3: Table Of Contents
POWER ON RESET ......................... 39 WATCHDOG RESET ........................39 BROWN OUT RESET ........................39 THE SYSTEM OPERATING VOLTAGE ..................40 LOW VOLTAGE DETECTOR (LVD) .................... 40 BROWN OUT RESET IMPROVEMENT ..................42 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 3... - Page 4 I/O PORT DATA REGISTER ......................75 TIMERS ..............................76 WATCHDOG TIMER ........................76 T0 8- ........................78 BIT BASIC TIMER 8.2.1 OVERVIEW ..........................78 8.2.2 T0 Timer Operation ........................79 8.2.3 T0M MODE REGISTER ......................80 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 4...
- Page 5 PROGRAMMING TOOL 14.3 PROGRAMMING PIN MAPPING: ....................114 MARKING DEFINITION ....................... 115 15.1 INTRODUCTION .......................... 115 15.2 MARKING INDETIFICATION SYSTEM ..................115 15.3 MARKING EXAMPLE ......................... 115 15.4 DATECODE SYSTEM ........................116 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 5...
- Page 6 SN8P2318 Series C-type LCD, RFC 8-Bit Micro-Controller PACKAGE INFORMATION ......................117 16.1 LQFP 64 PIN ..........................117 16.2 LQFP 48 PIN ..........................118 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 6...
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Page 7: Product Overview
LQFP 64 pin Features Selection Table Timer LCD Driver Ext. CHIP Stack Package C-type R-type SN8P2308 4K*16 128*8 2-ch 4*32 LQFP64 SN8P2318 4K*16 128*8 5-ch 4*32 LQFP64 SN8P2317 4K*16 128*8 5-ch 4*21 LQFP48 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 7... -
Page 8: System Block Diagram
NC 13 36 SEG13 NC 14 35 SEG14 NC 15 34 SEG15 P5.4/PWM0 16 33 SEG16/P3.7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 8... - Page 9 P1.3/RFC3 8 29 SEG12 P1.4/RFC4 9 28 SEG13 P1.5 10 27 SEG14 P1.6/RFCOUT 11 26 SEG15 P5.4/PWM0 12 25 SEG20/P3.3 13 14 15 16 17 18 19 20 21 22 23 24 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 9...
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Page 10: Pin Descriptions
SEG[31:24]: LCD segment output pins. P3[7:0]/ P3[7:0]: Bi-direction pin. No Schmitt trigger structure. Built-in pull-up resisters. SEG[23:16] SEG[23:16]: LCD segment output pins. SEG[15:0] SEG[15:0]: LCD segment output pins. COM[3:0] COM[3:0]: LCD common 0~3 output pins. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 10... -
Page 11: Pin Circuit Diagrams
Specific Output Function Control Bit LCD SEG shared pin structure: Pull-Up Resistor LCD SEG Control PnUR Register IO Input Bus Output Output Bus Latch LCD Segment LCD Segment Signal Generator Signal Version 1.5 SONiX TECHNOLOGY CO., LTD Page 11... - Page 12 Pin Name Oscillator Code Option Description 32K X’tal LXOUT Oscillator output pin. Flosc signal output pin to measure RC frequency for adjusting RC parameters. Low_Clk Code Option 32K X’tal Driver Flosc signal Version 1.5 SONiX TECHNOLOGY CO., LTD Page 12...
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Page 13: Central Processor Unit (Cpu)
The Interrupt vector is the head of interrupt service routine when any interrupt occurring. The General purpose area is main program area including main loop, sub-routines and data table. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 13... -
Page 14: Reset Vector (0000H)
Example: Defining Reset Vector ; 0000H START ; Jump to user program address. … START: ; 0010H, The head of user program. … ; User program … ENDP ; End of program Version 1.5 SONiX TECHNOLOGY CO., LTD Page 14... -
Page 15: Interrupt Vector (0008H)
RETI ; End of interrupt service routine … START: ; The head of user program. … ; User program … START ; End of user program … ENDP ; End of program Version 1.5 SONiX TECHNOLOGY CO., LTD Page 15... - Page 16 ; End of program. Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
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Page 17: Look-Up Table Description
Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Example: INC_YZ macro. INC_YZ MACRO INCMS ; Z+1 ; Not overflow INCMS ; Y+1 ; Not overflow ENDM Version 1.5 SONiX TECHNOLOGY CO., LTD Page 17... - Page 18 ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 … TABLE1: 0035H ; To define a word (16 bits) data. 5105H 2012H … Version 1.5 SONiX TECHNOLOGY CO., LTD Page 18...
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Page 19: Jump Table Description
; ACC = 3, jump to A3POINT SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size. - Page 20 ; ACC = 1, jump to A1POINT 0X0102 A2POINT ; ACC = 2, jump to A2POINT 0X0103 A3POINT ; ACC = 3, jump to A3POINT 0X0104 A4POINT ; ACC = 4, jump to A4POINT Version 1.5 SONiX TECHNOLOGY CO., LTD Page 20...
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Page 21: Checksum Calculation
; If Not jump to checksum calculate CHECKSUM_END ; If Yes checksum calculated is done. Y_ADD_1: INCMS ; Increase Y ; Jump to checksum calculate CHECKSUM_END: … … END_USER_CODE: ; Label of program end Version 1.5 SONiX TECHNOLOGY CO., LTD Page 21... -
Page 22: Data Memory (Ram)
“ 0FFh End of Bank 0 The 128-byte general purpose RAM is in Bank 0. Sonix provides “Bank 0” type instructions (e.g. b0mov, b0add, b0bts1, b0bset…) to control Bank 0 RAM in non-zero RAM bank condition directly. 2.2.1 SYSTEM REGISTER 2.2.1.1... -
Page 23: Bit Definition Of System Register
0F8H S3PC7 S3PC6 S3PC5 S3PC4 S3PC3 S3PC2 S3PC1 S3PC0 STK3L 0F9H S3PC11 S3PC10 S3PC9 S3PC8 STK3H 0FAH S2PC7 S2PC6 S2PC5 S2PC4 S2PC3 S2PC2 S2PC1 S2PC0 STK2L 0FBH S2PC11 S2PC10 S2PC9 S2PC8 STK2H Version 1.5 SONiX TECHNOLOGY CO., LTD Page 23... - Page 24 2. All of register names had been declared in SN8ASM assembler. 3. One-bit name had been declared in SN8ASM assembler with “F” prefix code. 4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 24...
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Page 25: Accumulator
“PUSH”, “POP” save and load ACC, PFLAG data into buffers. Example: Protect ACC and working registers. INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 25... -
Page 26: Program Flag
1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero. Note: Refer to instruction set table for detailed information of C, DC and Z flags. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 26... -
Page 27: Program Counter
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. CMPRS A, #12H ; To skip, if ACC = 12H. C0STEP ; Else jump to C0STEP. … … C0STEP: Version 1.5 SONiX TECHNOLOGY CO., LTD Page 27... - Page 28 DECS BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: DECMS instruction: DECMS BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: Version 1.5 SONiX TECHNOLOGY CO., LTD Page 28...
- Page 29 ; If ACC = 0, jump to A0POINT A1POINT ; ACC = 1, jump to A1POINT A2POINT ; ACC = 2, jump to A2POINT A3POINT ; ACC = 3, jump to A3POINT … … Version 1.5 SONiX TECHNOLOGY CO., LTD Page 29...
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Page 30: H, L Registers
; Clear @HL to be zero ; L – 1, if L = 0, finish the routine DECMS CLR_HL_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … … Version 1.5 SONiX TECHNOLOGY CO., LTD Page 30... -
Page 31: Y, Z Registers
Bit 2 Bit 1 Bit 0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Read/Write After reset Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 31... -
Page 32: Addressing Mode
; To clear Y register to access RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 32... -
Page 33: Stack Operation
STKP = 5 STK5H STK5L STKP STKP STKP = 4 STK4H STK4L STKP = 3 STK3H STK3L STKP = 2 STK2H STK2L STKP = 1 STK1H STK1L STKP = 0 STK0H STK0L Version 1.5 SONiX TECHNOLOGY CO., LTD Page 33... -
Page 34: Stack Registers
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKnL SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0 Read/Write After reset STKn = STKnH , STKnL (n = 7 ~ 0) Version 1.5 SONiX TECHNOLOGY CO., LTD Page 34... -
Page 35: Stack Operation Example
STKP Register Stack Buffer Stack Level Description STKPB2 STKPB1 STKPB0 High Byte Low Byte STK7H STK7L STK6H STK6L STK5H STK5L STK4H STK4L STK3H STK3L STK2H STK2L STK1H STK1L STK0H STK0L Free Free Version 1.5 SONiX TECHNOLOGY CO., LTD Page 35... -
Page 36: Code Option Table
Fcpu means instruction cycle of normal mode (high clock). In slow mode, the system clock source is external low speed 32KHz oscillator connected to LXIN/LXOUT pins. The Fcpu of slow mode isn’t controlled by Fcpu code option and fixed Flosc/4. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 36... -
Page 37: Reset_Pin Code Option
Note: When code option High_Clk = PLL_16M / Low_Clk = 32K X’tal and watchdog = Enable / Always_On, the system is unused with sleep mode (support green mode ). Version 1.5 SONiX TECHNOLOGY CO., LTD Page 37... -
Page 38: Reset
High Detect Low Detect Watchdog Overflow Watchdog Normal Run Watchdog Reset Watchdog Stop System Normal Run System Status System Stop Power On External Watchdog Delay Time Reset Delay Reset Delay Time Time Version 1.5 SONiX TECHNOLOGY CO., LTD Page 38... -
Page 39: Power On Reset
(e.g. EFT interference or external loading changed). The brown out reset would make the system not work well or executing program error. System Work Well Area System Work Error Area Brown Out Reset Diagram Version 1.5 SONiX TECHNOLOGY CO., LTD Page 39... -
Page 40: The System Operating Voltage
The dead-band definition is the system minimum operating voltage above the system reset voltage. 3.6 LOW VOLTAGE DETECTOR (LVD) LVD Detect Voltage Power Power is below LVD Detect Voltage and System Reset. System Normal Run System Status System Stop Power On Delay Time Version 1.5 SONiX TECHNOLOGY CO., LTD Page 40... - Page 41 C-type LCD, RFC 8-Bit Micro-Controller The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by each MCU.
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Page 42: Brown Out Reset Improvement
IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead-band. The external reset information is described in the next section. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 42... -
Page 43: External Reset
The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference. Note: The reset circuit is no any protection against unusual power or brown out reset. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 43... -
Page 44: Diode & Rc Reset Circuit
PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener specification. Select the right zener voltage to conform the application. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 44... -
Page 45: Voltage Bias Reset Circuit
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can improve all power variation. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 45... -
Page 46: System Clock
The system high-speed clock has internal and external two-type. The external high-speed clock includes 4MHz, 12MHz, crystal/ceramic and RC type. The internal high-speed clock is internal PLL 16MHz oscillator. These high-speed oscillators are selected by “High_Clk” code option. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 46... -
Page 47: High_Clk Code Option
C-type LCD, RFC 8-Bit Micro-Controller 4.3.1 HIGH_CLK CODE OPTION For difference clock functions, Sonix provides multi-type system high clock options controlled by “High_Clk” code option. The High_Clk code option defines the system oscillator types including PLL_16M, RC, 12M X’tal and 4M X’tal. -
Page 48: System Low-Speed Clock
10pF 10pF Note: Connect the Crystal/Ceramic and C as near as possible to the LXIN/LXOUT/VSS pins of micro-controller. Connect the C as near as possible to the VSS pin of micro-controller. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 48... -
Page 49: Oscm Register
Note: Do not measure the RC frequency directly from XIN pin of external high-speed RC mode and LXIN pin of external low-speed RC mode; the probe impendence will affect the RC frequency. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 49... -
Page 50: System Clock Timing
External Reset Pin Reset Timing Reset pin falling edge trigger system reset. External Reset Pin Reset pin returns to high status. External Reset Flag Oscillator Tcfg Tost Tosp Fcpu (Instruction Cycle) System is under reset status. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 50... - Page 51 Green Mode Wake-up Timing Edge trigger system wake-up. Wake-up Pin Falling Edge Wake-up Pin Rising Edge Timer overflow. Timer 0xFD 0xFE 0xFF 0x00 0x01 0x02 Oscillator Fcpu (Instruction Cycle) System inserts into green mode. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 51...
- Page 52 RC Oscillator Tost High-Speed Ceramic/Resonator Tost High-Speed Crystal Tost Low Speed RC (32K) Tost Low Speed Crystal (32K) Tost PLL 16MHz of Low Speed RC(32K) Tost PLL 16MHz of Low Speed Crystal(32K) Tost Version 1.5 SONiX TECHNOLOGY CO., LTD Page 52...
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Page 53: System Operation Mode
All active All active All inactive Wakeup source P0, P1, T0, Reset P0, P1, Reset EHOSC: External high-speed oscillator (XIN/XOUT). IHOSC: Internal high-speed PLL oscillator. ELOSC: External low-speed oscillator (LXIN/LXOUT). Version 1.5 SONiX TECHNOLOGY CO., LTD Page 53... -
Page 54: Normal Mode
Note: If the system is in normal mode, to set STPHX=1 to disable the high clock oscillator. The system is under no system clock condition. This condition makes the system stay as power down mode, and can be wake-up by P0, P1 level change trigger. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 54... -
Page 55: Green Mode
LCD, PWM and RFC functions active in green mode, but the timer can’t wake-up the system as overflow. Note: Sonix provides “GreenMode” macro to control green mode operation. It is necessary to use “GreenMode” macro to control system inserting green mode. -
Page 56: Operating Mode Control Macro
SN8P2318 Series C-type LCD, RFC 8-Bit Micro-Controller 5.6 OPERATING MODE CONTROL MACRO Sonix provides operating mode control macros to switch system operating mode easily. Macro Length Description SleepMode 1-word The system insets into Sleep Mode (Power Down Mode). GreenMode 3-word The system inserts into Green Mode. -
Page 57: Wakeup
The total wakeup time = 1 ms + oscillator start-up time The wake-up time of the external low-speed crystal type oscillator is as the following. The Wakeup time (32K_X’tal) = 1/Flosc * (2 +256) + low clock start-up time Version 1.5 SONiX TECHNOLOGY CO., LTD Page 57... - Page 58 +256) = 0.52 sec (32KHz crystal) The total wakeup time = 0.52 sec + oscillator start-up time Note: The high clock start-up time is depended on the VDD and oscillator type of high clock. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 58...
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Page 59: P1W Wakeup Control Register
Bit 0 P16W P15W P14W P13W P12W P11W P10W Read/Write After reset Bit[6:0] P10W~P16W: Port 1 wakeup function control bits. 0 = Disable P1n wakeup function. 1 = Enable P1n wakeup function. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 59... -
Page 60: Interrupt
T0IRQ CMnM Enable T0 Time Out 2-Bit TC0IRQ TC0 Time Out Gating Global Interrupt Request Signal T1IRQ Latchs T1 Time Out Note: The GIE bit must enable during all interrupt operation. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 60... -
Page 61: Inten Interrupt Enable Register
0 = Disable TC0 interrupt function. 1 = Enable TC0 interrupt function. Bit 6 T1IEN: T1 timer interrupt control bit. 0 = Disable T1 interrupt function. 1 = Enable T1 interrupt function. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 61... -
Page 62: Intrq Interrupt Request Register
TC0IRQ: TC0 timer interrupt request flag. 0 = None TC0 interrupt request. 1 = TC0 interrupt request. Bit 6 T1IRQ: T1 timer interrupt request flag. 0 = None T1 interrupt request. 1 = T1 interrupt request. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 62... -
Page 63: Gie Global Interrupt Operation
0 = Disable global interrupt. 1 = Enable global interrupt. Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE Note: The GIE bit must enable during all interrupt operation. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 63... -
Page 64: Push, Pop Routine
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine executed. START INT_SERVICE START: … INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector … ENDP Version 1.5 SONiX TECHNOLOGY CO., LTD Page 64... -
Page 65: External Interrupt Operation (Int0)
; P00IRQ = 0, exit interrupt vector B0BCLR FP00IRQ ; Reset P00IRQ … ; INT0 interrupt service routine EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 65... -
Page 66: Int1 (P0.1) Interrupt Operation
; P01IRQ = 0, exit interrupt vector B0BCLR FP01IRQ ; Reset P01IRQ … ; INT1 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 66... -
Page 67: T0 Interrupt Operation
A, #64H B0MOV T0C, A ; Reset T0C. … ; T0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 67... -
Page 68: Tc0 Interrupt Operation
A, #64H B0MOV TC0C, A ; Reset TC0C. … ; TC0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 68... -
Page 69: T1 Interrupt Operation
; Save pulse width. B0MOV A, T1CH B0MOV T1CHBUF, A T1CH T1CL … ; T1 interrupt service routine … EXIT_INT: ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 69... -
Page 70: Multi-Interrupt Operation
B0BTS0 FT1IRQ ; Check T1IRQ INTT1 ; Jump to T1 interrupt service routine … … INT_EXIT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.5 SONiX TECHNOLOGY CO., LTD Page 70... -
Page 71: I/O Port
P1.4 P1.6 RFCOUT RFCENB=1, RFCOUT=1 PWM0 TC0ENB=1, PWMOUT=1 P5.4 SEG[28:31] PSEG[2:0]=000b P2[3:0] P2[7:4] SEG[24:27] PSEG[2:0]=000b/001b SEG[20:23] PSEG[2:0]=000b/001b/010b P3[3:0] SEG[16:19] PSEG[2:0]=000b/001b/010b/011b P3[7:4] * DC: Digital Characteristic. AC: Analog Characteristic. HV: High Voltage Characteristic. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 71... -
Page 72: I/O Port Mode
A, #0FFH ; Set all ports to be output mode. B0MOV P0M, A B0MOV P1M,A B0BCLR P1M.0 ; Set P1.0 to be input mode. B0BSET P1M.0 ; Set P1.0 to be output mode. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 72... - Page 73 … B0BCLR P2M.0 ; Set P2.0 to input mode. B0BCLR P3M.0 ; Set P3.0 to input mode. ;Disable P2.0~P2.7 and P3.0~P3.7 GPIO function. B0BCLR FPSEG2 ; Set PSEG[2:0]=000b B0BCLR FPSEG1 B0BCLR FPSEG0 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 73...
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Page 74: I/O Pull Up Register
Note: P0.3 is input only pin and without pull-up resister. The P0UR.3 is undefined. Example: I/O Pull up Register A, #0FFH ; Enable Port0, 1 Pull-up register, B0MOV P0UR, A B0MOV P1UR,A Version 1.5 SONiX TECHNOLOGY CO., LTD Page 74... -
Page 75: I/O Port Data Register
; Write data FFH to all Port. B0MOV P0, A B0MOV P1, A Example: Write one bit data to output port. ; Set P1.0 to be “1”. B0BSET P1.0 ; Set P1.0 to be “0”. B0BCLR P1.0 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 75... -
Page 76: Timers
; Clear the watchdog timer. B0MOV WDTR, A … CALL SUB1 CALL SUB2 … MAIN Example: Clear watchdog timer by “@RST_WDT” macro of Sonix IDE. Main: @RST_WDT ; Clear the watchdog timer. … CALL SUB1 CALL SUB2 … MAIN Version 1.5... - Page 77 ; I/O and RAM are correct. Clear watchdog timer and ; execute program. A, #5AH ; Clear the watchdog timer. B0MOV WDTR, A … CALL SUB1 CALL SUB2 … … … MAIN Version 1.5 SONiX TECHNOLOGY CO., LTD Page 77...
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Page 78: T0 8-Bit Basic Timer
T0C 8-Bit Binary Up Counting Counter (T0 timer overflow.) Ext. 32K ÷ 64 (LXIN, LXOUT) CPUM0,1 Note: In RTC mode, the T0 interval time is fixed at 0.5 sec and T0C is 256 counts. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 78... -
Page 79: T0 Timer Operation
16.384 65.536 001b Fcpu/128 8.192 32.768 010b Fcpu/64 4.096 16.384 011b Fcpu/32 2.048 8.192 100b Fcpu/16 1.024 4.096 101b Fcpu/8 0.512 2.048 110b Fcpu/4 0.256 1.024 111b Fcpu/2 0.128 0.512 32768Hz/64 1.953 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 79... -
Page 80: T0M Mode Register
* 4 * 10 / 4 / 128) = B2H Note: In RTC mode, T0C is 256 counts and generatesT0 0.5 sec interval time. Don’t change T0C value in RTC mode. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 80... -
Page 81: T0 Timer Operation Example
; Set T0 RTC function. B0BSET FT0TB ; Clear T0C. ; Clear T0IRQ B0BCLR FT0IRQ ; Enable T0 timer and interrupt function. B0BSET FT0IEN ; Enable T0 interrupt function. B0BSET FT0ENB ; Enable T0 timer. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 81... -
Page 82: Tc0 8-Bit Timer/Counter
Data Buffer Reload Value TC0CKS0 Load TC0CKS1 TC0ENB Fcpu Fhosc TC0 Time Out TC0C 8-Bit Binary Up Counting Counter PWM0OUT INT0 (Schmitter Trigger) P5.4 Pin CPUM0,1 Compare TC0D Data Buffer P5.4 GPIO Version 1.5 SONiX TECHNOLOGY CO., LTD Page 82... -
Page 83: Tc0 Timer Operation
Unit (us) 000b Fcpu/128 4.096 001b Fcpu/64 2.048 010b Fcpu/32 1.024 011b Fcpu/16 0.512 100b Fcpu/8 0.256 101b Fcpu/4 0.128 110b Fcpu/2 0.064 0.25 111b Fcpu/1 0.032 0.125 useless Fhosc 0.016 0.0625 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 83... -
Page 84: Tc0M Mode Register
TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0 Read/Write After reset The equation of TC0C initial value is as following. TC0C initial value = 256 - (TC0 interrupt interval time * TC0 clock rate) Version 1.5 SONiX TECHNOLOGY CO., LTD Page 84... -
Page 85: Tc0R Auto-Reload Register
3.33ms. TC0D initial value = B2H + (PWM high pulse width period / TC0 clock rate) = B2H + (3.33ms * 16MHz / 16 / 128) = B2H + 1AH = CCH Version 1.5 SONiX TECHNOLOGY CO., LTD Page 85... -
Page 86: Tc0 Event Counter
PWM exchanges to low status. PWM outputs high status. PWM exchanges to high status. TC0R TC0R TC0D TC0D TC0R TC0R TC0R TC0D 0xFD 0xFE 0xFF TC0R TC0C PWM Output One complete cycle of PWM. Next cycle. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 86... -
Page 87: Tc0 Timer Operation Example
; TC0C must be equal to TC0R. B0MOV TC0C, A B0MOV TC0R, A ; Clear TC0IRQ B0BCLR FTC0IRQ ; Enable TC0 timer and interrupt function. B0BSET FTC0IEN ; Enable TC0 interrupt function. B0BSET FTC0ENB ; Enable TC0 timer. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 87... - Page 88 ; Set TC0D register for PWM duty. A, #value2 ; TC0D must be greater than TC0R. B0MOV TC0D, A ; Enable PWM and TC0 timer. B0BSET FTC0ENB ; Enable TC0 timer. B0BSET FPWM0OUT ; Enable PWM. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 88...
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Page 89: T1 16-Bit Timer With Capture Timer Function
Fhosc (Capture timer stop) CPUM0,1 P0.2/T1IN CPTStart CPTG[1:0] = 00, Disable. 01/10/11 = Enable. RFC Output Signal CPTVC CPTStart T1VC Counter Overflow CPTCKS CPTG[1:0] T1VC 10-bit Event Counter, Binary Up Counting Counter Version 1.5 SONiX TECHNOLOGY CO., LTD Page 89... -
Page 90: T1 Timer Operation
1048.576 4194.304 010b Fcpu/32 524.288 2097.152 011b Fcpu/16 262.144 1048.576 100b Fcpu/8 131.072 524.288 101b Fcpu/4 65.536 262.144 110b Fcpu/2 32.768 131.072 111b Fcpu/1 16.384 0.25 65.536 Fhosc/1 4.096 0.0625 16.384 0.25 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 90... -
Page 91: T1M Mode Register
000 = Fcpu/128, 001 = Fcpu/64, 010 = Fcpu/32, 011 = Fcpu/16, 100 = Fcpu/8, 101 = Fcpu/4, 110 = Fcpu/2,111 = Fcpu/1. Bit 3 T1CKS: T1 clock source control bit. 0 = Fcpu divided by T1rate[2:0]. 1 = Fhosc. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 91... -
Page 92: T1Ch, T1Cl 16-Bit Counting Registers
T1 16-bit counter initial value = 65536 - (T1 interval time * input clock) = 65536 - (500ms * 16MHz / 16 / 128) = 65536 - (500*10 * 16 * 10 / 16 / 128) = F0BDH (T1CH = F0H, T1CL = BDH) Version 1.5 SONiX TECHNOLOGY CO., LTD Page 92... -
Page 93: T1 Cpature Timer Operation
The cycle measurement is using rising edge to start and stop T1 16-bit counter. If set CPTStart bit at high or low pulse duration, the capture timer will measure next cycle until the rising edge occurrence. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 93... -
Page 94: Capture Timer Control Registers
T1 stops counting. CPTStart = 0 Un-know T1 16-bit Counter Data 0x???? T1 is counting. “n” is the period of (256-n) cycle of input signals. Read it by program through T1CH, T1CL 0x0000 registers. Initialization Version 1.5 SONiX TECHNOLOGY CO., LTD Page 94... -
Page 95: T1Vch, T1Vcl 10-Bit Event Counter Registers
Read T1 event counter buffer sequence is to read T1VCL first, and then read T1VCH. Write T1 event counter buffer sequence is to write T1VCH first, and then write T1VCL. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 95... -
Page 96: T1 Timer Operation Example
; Enable T1 timer, interrupt function and T1 capture timer function. B0BSET FT1IEN ; Enable T1 interrupt function. B0BSET FT1ENB ; Enable T1 timer. ; Set capture timer start bit. B0BSET FCPTStart Version 1.5 SONiX TECHNOLOGY CO., LTD Page 96... - Page 97 ; Enable T1 timer, interrupt function and T1 capture timer function. B0BSET FT1IEN ; Enable T1 interrupt function. B0BSET FT1ENB ; Enable T1 timer. B0BSET FCPTVC ; Enable T1 event counter function. ; Set capture timer start bit. B0BSET FCPTStart Version 1.5 SONiX TECHNOLOGY CO., LTD Page 97...
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Page 98: Resistance To Frequrncy Converter (Rfc)
RFCOUT pin: RFC output pin is shared with GPIO controlled by RFCOUT bit. RFC output pin outputs RFC oscillating signal through RFC oscillator generator processing. The signal also inputs to T1 capture timer. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 98... -
Page 99: Rfc Application Circuit
RFC converting result. The RFC clock can be T1 clock source to measure RFC converting value by frequency measurement and pulse width measurement. The RFC clock also can output to RFCOUT pin (P1.6) when RFCOUT =1. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 99... -
Page 100: Rfcm Register
2. RFCM.4 must be set as “1” by program through MOV/B0MOV instruction because the bit is write only type. 3. RFCM.5 must be set as “0” by program through MOV/B0MOV instruction because the bit is write only type. 4. We strongly recommend controlling RFCM register through MOV/B0MOV instructions. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 100... -
Page 101: Rfc Operation Example
B0BSET FCPTStart ; Start to measure RFC frequency. ; Check T1IRQ=1. Chk_T1IRQ: B0BTS1 FT1IRQ ; Check T1IRQ=1. Chk_T1IRQ B0MOV A, T1CL ; The end of RFC measurement. … B0MOV A, T1CH … Version 1.5 SONiX TECHNOLOGY CO., LTD Page 101... -
Page 102: 4X32 Lcd Driver
BIAS: LCD bias control bit. 0 = 1/3 bias (C type and R type). 1 = 1/2 bias (R type only). Bit 0 LCDENB: LCD control bit. 0 = Disable. 1 = Enable. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 102... -
Page 103: C-Type Lcd Mode
; Enable charge pump. B0BSET FVLCDCP ; Enable LCD charge-pump and LCD is switched to ; C-type mode. ; Enable LCD driver. B0BSET FLCDENB ; Enable LCD driver.. ; LCD picture process. … … Version 1.5 SONiX TECHNOLOGY CO., LTD Page 103... -
Page 104: R-Type Lcd Mode
; Set C-type LCD. ; “n” selects bias. A, #000mmmn0B ; “mmm” controls P2/P3 LCD shared pins. B0MOV LCDM ; Enable LCD driver. B0BSET FLCDENB ; Enable LCD driver.. ; LCD picture process. … … Version 1.5 SONiX TECHNOLOGY CO., LTD Page 104... -
Page 105: Lcd Ram Map
; Clear COM1=1 of SEG 1. … A, #0 ; Switch to RAM bank 0. B0MOV RBANK, A Note: Access RAM data of bank 0 (system registers and user define RAM 0x0000~0x007F) is using “B0xxx” instructions. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 105... -
Page 106: Lcd Waveform
VLCD COM2 1/2*VLCD VLCD 2/3*VLCD COM2 1/3*VLCD VLCD COM3 1/2*VLCD VLCD 2/3*VLCD COM3 1/3*VLCD VLCD SEG0 (1010b) 1/2*VLCD VLCD 2/3*VLCD SEG0 (1010b) 1/3*VLCD VLCD SEG0 (0101b) 1/2*VLCD VLCD 2/3*VLCD SEG0 (0101b) 1/3*VLCD Version 1.5 SONiX TECHNOLOGY CO., LTD Page 106... -
Page 107: Instruction Table
Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1. 2. If branch condition is true then “S = 1”, otherwise “S = 0”. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 107... -
Page 108: Electrical Characteristic
Vdet0 Low voltage reset level. 25 LVD Voltage Vdet1 Low voltage reset/indicator level. 25 Vdet2 Low voltage reset/indicator level. 25 “ ” These parameters are for design reference, not tested. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 108... -
Page 109: Characteristic Graphs
The Graphs in this section are for design guidance, not tested or guaranteed. In some graphs, the data presented are outside specified operating range. This is for information only and devices are guaranteed to operate properly only within the specified range (-40℃~+85℃ curves are for design reference). Version 1.5 SONiX TECHNOLOGY CO., LTD Page 109... -
Page 110: Development Tool
Writer transition board: SN8P2318 13.1 SN8P2318 EV-KIT SONIX provides SN8P2318 MCU which includes LCD and RFC functions. These functions aren’t built in SN8ICE2K Plus 2. To emulate the functions must be through SN8P2318 real chip. The real chip provides an EV-KIT to achieve LCD and RFC functions emulations. -
Page 111: Ice And Ev-Kit Application Notic
2. Connect EV-KIT’s JP1/JP2 to ICE’s JP3/CON1. 3. Turn on SN8ICE2K Plus 2 power switch to start emulation. 4. If the power indicator (LED D1) doesn’t light, the EV-kit occurs some mistakes. Please contact SONIX’s agent for maintain service. 5. It is necessary to connect 16MHz crystal in ICE for IHRC_16M mode emulation. SN8ICE2K Plus 2 doesn’t support over 8-mips instruction cycle, but real chip does 6. -
Page 112: Otp Programming Pin
JP1 for Writer transition board DIP13 DIP36 JP2 for dice and >48 pin package DIP14 DIP35 DIP15 DIP34 DIP16 DIP33 DIP17 DIP32 DIP18 DIP31 DIP19 DIP30 DIP20 DIP29 DIP21 DIP28 DIP22 DIP27 DIP23 DIP26 DIP24 DIP25 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 112... -
Page 113: Sn8P2317 / Sn8P2318 Otp Programming Tool
14.2 SN8P2317 / SN8P2318 OTP PROGRAMMING TOOL WR080 is writer board for SN8P2318 LQFP64 OTP programming socket connection. MP125 is transition board for SN8P2317 LQFP48 OTP programming socket. WR080 (Writer Board) Version 1.5 SONiX TECHNOLOGY CO., LTD Page 113... -
Page 114: Programming Pin Mapping
Writer Connector Assignment Assignment JP1/JP2 JP1/JP2 Pin Number Pin Name Pin Number Pin Name Pin Number Pin Number Pin Name 1/39 VDD/VLCD 64/54 VDD/VLCD P1.0 P1.0 P1.1 P1.1 P1.2 P1.2 ALSB/PDB P1.3 P1.3 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 114... -
Page 115: Marking Definition
Marking Definition 15.1 INTRODUCTION There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit MCU for order or obtain information. This definition is only for Blank OTP MCU. 15.2 MARKING INDETIFICATION SYSTEM SN8 X PART No. -
Page 116: Datecode System
..9=09 A=10 B=11 ..1=January Month 2=February ..9=September A=October B=November C=December 03= 2003 Year 04= 2004 05= 2005 06= 2006 ..Version 1.5 SONiX TECHNOLOGY CO., LTD Page 116... -
Page 117: Package Information
0.003 0.080 0.003 0.008 0.080 0.200 0.030 0.750 θ° 0° 3.5° 7° 0° 3.5° 7° θ1° 0° 0° θ2° 11° 12° 13° 11° 12° 13° θ3° 11° 12° 13° 11° 12° 13° Version 1.5 SONiX TECHNOLOGY CO., LTD Page 117... -
Page 118: Lqfp 48 Pin
0.35 BSC 9.00 BSC 0.27 BSC 7.00 BSC 0.35 BSC 9.00 BSC 0.27 BSC 7.00 BSC 0.02 BSC 0.5 BSC 0.01 0.01 0.17 0.27 0.02 0.03 0.45 0.75 0.04 REF 1 REF Version 1.5 SONiX TECHNOLOGY CO., LTD Page 118... - Page 119 SONIX product could create a situation where personal injury or death may occur.
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