SONIX SN8P2977 User Manual
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SONIX SN8P2977 User Manual

8-bit micro-controller
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SN8P2977
USER'S MANUAL
Specification V1.7
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
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8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
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SN8P2977
V1.7

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Summary of Contents for SONIX SN8P2977

  • Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.

  • Page 2: Amendent History

    Ver1.6 2017.09 3.Add Package information(Ver1.5) to FEATURES(Chapter 1.3) 4.Modify QFN32 package type of name to 2975 from 2977.(page 14) Ver1.7 2017.09 1.Modify the name of package type in SSOP20 from SN8P2972 to SN8P2973.(page14) V1.7 SONiX TECHNOLOGY CO., LTD Page 2...

  • Page 3: Table Of Contents

    WATCHDOG RESET ..........................44 BROWN OUT RESET ..........................44 3.4.1 BROWN OUT DESCRIPTION ......................44 3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION ............... 45 3.4.3 BROWN OUT RESET IMPROVEMENT ..................45 SYSTEM CLOCK ............................47 V1.7 SONiX TECHNOLOGY CO., LTD Page 3...
  • Page 4 8.3.3 TC0X8, TC0GN FLAGS ........................77 8.3.4 TC0C COUNTING REGISTER ......................78 8.3.5 TC0R AUTO-LOAD REGISTER ....................... 80 8.3.6 TC0 CLOCK FREQUENCY OUTPUT (BUZZER) ................81 8.3.7 TC0 TIMER OPERATION SEQUENCE .................... 82 V1.7 SONiX TECHNOLOGY CO., LTD Page 4...
  • Page 5 CHS- Analog input signal channel selection Register ..............106 13.4.2 AMPM- Amplifier Mode Control Register ..................108 13.5 (TS) ........................109 EMPERATURE ENSOR 13.6 24-B (ADC) ................... 111 NALOG TO IGITAL ONVERTER 13.6.1 Analog Inputs and Voltage Operation Range ................111 V1.7 SONiX TECHNOLOGY CO., LTD Page 5...
  • Page 6 MULATION 16.4.1 INTRODUCTION ......................... 131 16.4.2 SN8ICE2K_Plus_II Hardware Setting Notice for SN2977 EV-Kit ..........131 16.4.3 SN8P2977 EV Board DESCRIPTION ..................132 16.4.4 EV BOARD SETTING ......................... 133 16.4.5 Notice for EV Emulation ....................... 133 ELECTRICAL CHARACTERISTIC ......................134 17.1 ABSOLUTE MAXIMUM RATING ......................
  • Page 7 SN8P2977 8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC 19.3 MARKING EXAMPLE ......................... 145 19.4 DATECODE SYSTEM .......................... 145 V1.7 SONiX TECHNOLOGY CO., LTD Page 7...

  • Page 8: Product Overview

    T0 TC0 TC1 SN8P2967 2K*16 192*8 4*12 V 10 20-bit DIP48/SSOP48/LQFP48 SN8P2962 2K*16 192*8 10 20-bit SOP18 SN8P2977 4K*16 256*8 4*16 V 26 24-bit DIP48/SSOP48/LQFP48 SN8P2972 4K*16 256*8 26 24-bit SOP18 Table 1-1 Selection table of SN8Px9x7 serial 1.2 MIGRATION TABLEUART...

  • Page 9: Features

    Sleep mode: Both high and low clock stop ADC Offset selection: (-1/4, -2/4, -3/4) * Vref ) ◆ ADC Interrupt and Green Mode wakeup function Package Dice/LQFP48/DIP48/SSOP48/QFN32 4-ADC channels configuration: TSSOP28/SSOP20/SOP18/SOP16 - Two fully differential channels - Four single channel V1.7 SONiX TECHNOLOGY CO., LTD Page 9...

  • Page 10: System Block Diagram

    TIMING GENERATOR Low Battery Comparator Regulator AVDDR/AVE PGIA AI1~ AI4 UART UTX,URX SYSTEM REGISTERS 20-BIT ADC 20-BIT ADC INTERRUPT CONTROL TIMER & COUNTER Internal Reference VLCD/VDD Detect Figure 1-1 Simplified system block diagram V1.7 SONiX TECHNOLOGY CO., LTD Page 10...

  • Page 11: Pin Assignment

    P26/SEG9 SEG3/P34 P25/SEG10 SEG2/P35 P24/SEG11 SEG1/P36 P23/SEG12 SEG0/P37 P22/SEG13 COM3 P21/SEG14 COM2 P20/SEG15 COM1 COM0 VLCD/VPP DVDD DVSS P07/LXOUT AVDDR P06/LXIN P05/RX AVSS P04/PDB/TX AVDD P03/SHIFTDATA/Buzzer P02/OTPCLK P01/INT1/PGCLK R+/AI3 P00/INT0 R-/AI4 P11/PWM0 P10/LBT V1.7 SONiX TECHNOLOGY CO., LTD Page 11...
  • Page 12 P36/SEG1 1 O SEG14/P21 P37/SEG0 2 SEG15/P20 COM3 COM2 COM1 DVDD COM0 DVSS SN8P2977 VLCD/VPP P07/LXOUT AVDDR P06/LXIN P05/RX AVSS P04/TX AVDD P03/Buzzer 13 14 15 16 17 18 19 20 21 22 23 24 V1.7 SONiX TECHNOLOGY CO., LTD Page 12...
  • Page 13 SEG7/P30 2975 SEG8/P27 SEG9/P26 INT1/P0.1 SEG10/P25 P0.2 SEG11/P24 SN8P2974 TSSOP28 COM2 COM3 COM1 P37/SEG0 COM0 P36/SEG1 VLCD/VPP P35/SEG2 AVDDR P34/SEG3 P33/SEG4 P32/SEG5 P31/SEG6 P30/SEG7 INT1/P01 P27/SEG8 P26/SEG9 Buzzer/P03 P25/SEG10 TX/P04 P24/SEG11 P22/SEG13 P23/SEG12 V1.7 SONiX TECHNOLOGY CO., LTD Page 13...
  • Page 14 DVSS SN8P2972 SOP18 VLCD/VPP DVDD AVDDR DVSS AVSS P07/LXOUT AVDD P06/LXIN P05/RX P04/TX P10/LBT P03/Buzzer P11/PWM0 P00/INT0 P01/INT1 SN8P2971 SOP16 VLCD/VPP DVDD AVDDR DVSS P07/LXOUT P06/LXIN P1.0/LBT P05/RX P1.1/PWM0 P04/TX P0.0/INT0 P03/Buzzer P0.1/INT1 V1.7 SONiX TECHNOLOGY CO., LTD Page 14...

  • Page 15: Pin Descriptions

    IO share with LXIN 32768 Oscillator. IO share with LXOUT 32768 Oscillator. P1 [1:0] P10~P11 bi-direction pins / Built-in pull-up resisters (optional) I/O shire with LBT function (Low battery detect, comparator input) I/O shire with PWM0/TC0OUT. V1.7 SONiX TECHNOLOGY CO., LTD Page 15...

  • Page 16: Pin Circuit Diagrams

    1.7 PIN CIRCUIT DIAGRAMS Port 0, Port 1 structure: Pull-Up PnM, PnUR Input Bus Output Output Bus Latch Port 2, Port 3 structure: Pull-Up PnSEG PnM, PnUR Input Bus Output Bus Output Latch LCD-SEG Function V1.7 SONiX TECHNOLOGY CO., LTD Page 16...

  • Page 17: Central Processor Unit (Cpu)

    Jump to user start address 0004H 0005H Reserved 0006H 0007H 0008H Interrupt vector User interrupt vector 0009H User program 000FH 0010H General purpose area 0011H FFBH End of user program FFCH Reserved FFFH V1.7 SONiX TECHNOLOGY CO., LTD Page 17...

  • Page 18: Reset Vector (0000H)

    Example: Defining Reset Vector ; 0000H START ; Jump to user program address. … START: ; 0010H, The head of user program. … ; User program … ENDP ; End of program V1.7 SONiX TECHNOLOGY CO., LTD Page 18...
  • Page 19 ; Restore ACC from buffer. RETI ; End of interrupt service routine … START: ; The head of user program. … ; User program … START ; End of user program … ENDP ; End of program V1.7 SONiX TECHNOLOGY CO., LTD Page 19...
  • Page 20 ENDP ; End of program. Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: The address 0000H is a “JMP” instruction to make the program starts from the beginning.
  • Page 21 ; To define a word (16 bits) data. 5105H 2012H … The other example of look-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen. V1.7 SONiX TECHNOLOGY CO., LTD Page 21...
  • Page 22 ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 … TABLE1: 0035H ; To define a word (16 bits) data. 5105H 2012H … V1.7 SONiX TECHNOLOGY CO., LTD Page 22...
  • Page 23 When carry flag occurs after executing of “ADD PCL, A”, it will not affect PCH register. Users have to check if the jump table leaps over the ROM page boundary or the listing file generated by SONIX assembly software. If the jump table leaps over the ROM page boundary (e.g.
  • Page 24 8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
  • Page 25 ; If Not jump to checksum calculate CHECKSUM_END ; If Yes checksum calculated is done. Y_ADD_1: INCMS ; Increase Y ; Jump to checksum calculate CHECKSUM_END: … … END_USER_CODE: ; Label of program end V1.7 SONiX TECHNOLOGY CO., LTD Page 25...

  • Page 26: Code Option Table

    Enable Enable low power mode In high noisy environment, set Watch_Dog as “Always_On” is strongly recommended. Note1: Fcpu code option is only available for High Clock. Fcpu of slow mode is Flosc/4. Note2: V1.7 SONiX TECHNOLOGY CO., LTD Page 26...

  • Page 27: Data Memory (Ram)

    RAM Bank 1 Bank 1 General purpose area (Bank 1) 17FH End of Bank 1 Bank 15 F00H RAM Bank 15 LCD RAM Area … … (Bank 15) F0FH End of Bank 15 V1.7 SONiX TECHNOLOGY CO., LTD Page 27...

  • Page 28: System Register

    UART transmitted data buffer. URXD = UART received data buffer. @YZ = RAM YZ indirect addressing index pointer @HL = RAM HL indirect addressing index pointer STK0~STK7 Stack 0 ~ stack 7 Buffer V1.7 SONiX TECHNOLOGY CO., LTD Page 28...
  • Page 29 URCR2 URCR1 URCR0 URCR 0E5H UTXD7 UTXD6 UTXD5 UTXD4 UTXD3 UTXD2 UTXD1 UTXD0 UTXD 0E6H URXD7 URXD6 URXD5 URXD4 URXD3 URXD2 URXD1 URXD0 URXD 0E7H @YZ7 @YZ6 @YZ5 @YZ4 @YZ3 @YZ2 @YZ1 @YZ0 V1.7 SONiX TECHNOLOGY CO., LTD Page 29...
  • Page 30 2. All of register names had been declared in SN8ASM assembler. 3. One-bit name had been declared in SN8ASM assembler with “F” prefix code. 4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers. V1.7 SONiX TECHNOLOGY CO., LTD Page 30...

  • Page 31: Accumulator

    ; Restore ACC from buffer. RETI ; Exit interrupt service vector  Note: To save and re-load ACC data, users must use “B0XCH” instruction, or else the PFLAG Register might be modified by ACC operation. V1.7 SONiX TECHNOLOGY CO., LTD Page 31...

  • Page 32: Program Flag

    1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero.   Note: Refer to instruction set table for detailed information of C, DC and Z flags. V1.7 SONiX TECHNOLOGY CO., LTD Page 32...

  • Page 33: Program Counter

    If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. CMPRS A, #12H ; To skip, if ACC = 12H. C0STEP ; Else jump to C0STEP. … … C0STEP: V1.7 SONiX TECHNOLOGY CO., LTD Page 33...
  • Page 34 DECS instruction: DECS BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: DECMS instruction: DECMS BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: V1.7 SONiX TECHNOLOGY CO., LTD Page 34...

  • Page 35: Multi-Address Jumping

    ; If ACC = 0, jump to A0POINT A1POINT ; ACC = 1, jump to A1POINT A2POINT ; ACC = 2, jump to A2POINT A3POINT ; ACC = 3, jump to A3POINT … … V1.7 SONiX TECHNOLOGY CO., LTD Page 35...

  • Page 36: Y, Z Registers

    ; Clear @YZ to be zero ; Z – 1, if Z= 0, finish the routine DECMS CLR_YZ_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … V1.7 SONiX TECHNOLOGY CO., LTD Page 36...

  • Page 37: H, L Registers

    ; Clear @HL to be zero ; L – 1, if Z= 0, finish the routine DECMS CLR_HL_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … V1.7 SONiX TECHNOLOGY CO., LTD Page 37...

  • Page 38: R Registers

    Bit 3 Bit 2 Bit 1 Bit 0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Read/Write After reset  Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application. V1.7 SONiX TECHNOLOGY CO., LTD Page 38...

  • Page 39: Addressing Mode

    ; To clear Y register to access RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. V1.7 SONiX TECHNOLOGY CO., LTD Page 39...

  • Page 40: Stack Operation

    STKP = 5 STK5H STK5L STKP STKP STKP = 4 STK4H STK4L STKP = 3 STK3H STK3L STKP = 2 STK2H STK2L STKP = 1 STK1H STK1L STKP = 0 STK0H STK0L Version 1.7 SONiX TECHNOLOGY CO., LTD Page 40...

  • Page 41: Stack Registers

    Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKnL SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0 Read/Write After reset STKn = STKnH , STKnL (n = 7 ~ 0) Version 1.7 SONiX TECHNOLOGY CO., LTD Page 41...

  • Page 42: Stack Operation Example

    STKP Register Stack Buffer Stack Level Description STKPB2 STKPB1 STKPB0 High Byte Low Byte STK7H STK7L STK6H STK6L STK5H STK5L STK4H STK4L STK3H STK3L STK2H STK2L STK1H STK1L STK0H STK0L Free Free Version 1.7 SONiX TECHNOLOGY CO., LTD Page 42...

  • Page 43: Reset

    System initialization: All system registers is set as initial conditions and system is ready.  Oscillator warm up: Oscillator operation is successfully and supply to system clock.  Program executing: Power on sequence is finished and program executes from ORG 0. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 43...

  • Page 44: Watchdog Reset

    In AC power application, the DC power is regulated from AC power source. This kind of power usually couples with AC noise that makes the DC power dirty. Or the external loading is very heavy, e.g. driving motor. The loading operating Version 1.7 SONiX TECHNOLOGY CO., LTD Page 44...

  • Page 45: The System Operating Voltage Decsription

    Delay Time The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by each MCU.
  • Page 46 Adjust the system rate to the value and the system exits the dead-band issue. This way needs to modify whole program timing to fit the application requirement. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 46...

  • Page 47: System Clock

    Fhosc: System high clock source is from internal high RC (IHRC).  Flosc: System low clock source is from internal low RC (ILRC) or external 32k.  Fosc: System clock source.  Fcpu: Instruction cycle. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 47...

  • Page 48: Oscm Register

    Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal low-speed oscillator will be stopped. B0BSET FCPUM0 ; To stop IHRC and internal low-speed ; oscillator called power down mode (sleep mode). Version 1.7 SONiX TECHNOLOGY CO., LTD Page 48...

  • Page 49: System High Clock

    ; To stop IHRC and ILRC or 32k crystal called power down mode ; (sleep mode).   Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM) bits of OSCM register. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 49...

  • Page 50: System Clock Measurement

    ; Set P1.0 to be output mode for outputting Fcpu toggle signal. B0BSET P1.0 ; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P1.0 ; Measure the Fcpu frequency by oscilloscope. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 50...

  • Page 51: System Operation Mode

    Note_2: P04 and P05 can not wakeup IC when UART function enable. @Real chip  Note_3: When system into green mode with conditions of Code option IHRC_RTC function enable and P06/P07 still running, the system will be wakeup. @ICE MODE Version 1.7 SONiX TECHNOLOGY CO., LTD Page 51...

  • Page 52: System Mode Switching

    ; Set CPUM1 = 1.   Note: If T0 timer wakeup function is disabled in the green mode, the wakeup pin P0 can wakeup the system backs to the previous operation mode. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 52...
  • Page 53 ADC conversion complete.  Note_2: The ADC green mode wakeup function is disable when ADCEN=0 or stop high clock (STPHX=1) is set before into green mode. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 53...

  • Page 54: Wakeup

    The wakeup time is as the following. The wakeup time = 1/Fhosc * 64 = 8us (Fhosc = 8MHz) The total wakeup time = 8us + oscillator start-up time (5us) Version 1.7 SONiX TECHNOLOGY CO., LTD Page 54...

  • Page 55: Interrupt

    TC 0 Time Out Global Interrupt Request Signal UTX IRQ Gating Latchs UART Transmit END URXIRQ UART Receive END ADCIRQ ADC Out  Note: The GIE bit must enable during all interrupt operation. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 55...

  • Page 56: Inten Interrupt Enable Register

    P00IRQ: External P0.0 interrupt request bit. 0 = Non INT0 interrupt request. 1 = INT0 interrupt request. Bit 1 P01IRQ: External P0.1 interrupt request bit. 0 = Non INT1 interrupt request. 1 = INT1 interrupt request. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 56...

  • Page 57: Gie Global Interrupt Operation

    Bit [3:0] STKPBn: Stack pointer, n = 0~3.  Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE  Note: The GIE bit must enable during all interrupt operation. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 57...

  • Page 58: Push, Pop Routine

    ; Save PFLAG to PFLAGBUF buffer. … … B0MOV A, PFLAGBUF B0MOV PFLAG, A ; Load PFLAG from PFLAGBUF buffer. B0XCH A, ACCBUF ; Load ACC from ACCBUF buffer. RETI ; Exit interrupt service vector … ENDP Version 1.7 SONiX TECHNOLOGY CO., LTD Page 58...

  • Page 59: External Interrupt Operation

    ; P00IRQ = 0, exit interrupt vector B0BCLR FP00IRQ ; Reset P00IRQ … ; INT0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.7 SONiX TECHNOLOGY CO., LTD Page 59...

  • Page 60: Multi-Interrupt Operation

    ; Jump to TC0 interrupt service routine INTADCHK: ; Check ADC interrupt request B0BTS1 FADCIEN ; Check ADCIEN INTUTXCHK ; Jump check to next interrupt B0BTS0 FADCIRQ ; Check ADCIRQ INTADC ; Jump to ADC interrupt service routine Version 1.7 SONiX TECHNOLOGY CO., LTD Page 60...
  • Page 61 ; Jump to exit of IRQ B0BTS0 FURXIRQ ; Check URXIRQ INTURX ; Jump to UART RX interrupt service routine INT_EXIT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 1.7 SONiX TECHNOLOGY CO., LTD Page 61...

  • Page 62: I/O Port

    P26SEG P25SEG P24SEG P23SEG P22SEG P21SEG P20SEG After Reset Bit[7:0] P2nSEG: Port 2 function control bit 0 = Set as LCD function Pin. (SEG8~SEG15) 1 = Set as IO function Pin. (P27~P20) Version 1.7 SONiX TECHNOLOGY CO., LTD Page 62...
  • Page 63 ; Set P3.0 to be output mode.  Note: 1. P2/P3 I/O is share pin with LCD function 2. Port P2 ~ P3 is high-sink I/O Pin, It can drive seven-segment display. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 63...

  • Page 64: I/O Pull Up Register

    Pn0R~Pn7R: I/O port pull-up resistor control bit. (n = 0~1). 0 = Disable pull-up resistor. 1 = Enable pull-up resistor.  Note: PnUR is Write Only Register. Example: I/O Pull up Register A, #0FFH ; Enable Port1 Pull-up register, B0MOV P1UR,A Version 1.7 SONiX TECHNOLOGY CO., LTD Page 64...

  • Page 65: I/O Port Data Register

    ; Write data FFH to all Port. B0MOV P0, A B0MOV P1, A Example: Write one bit data to output port. ; Set P1.0 to be “1”. B0BSET P1.0 ; Set P1.0 to be “0”. B0BCLR P1.0 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 65...

  • Page 66: High-Sink Current I/O Port

    7.5 High-sink current I/O PORT The SN8P2977 has a built-in High sink I/O to support drive seven-segment display from port P2/P3 and it with typical 60mA current sinking capacity. when the pin is LOW, it can only accept that much current flowing to ground.

  • Page 67: Timers

    Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the main routine of the program. Main: A, #5AH ; Clear the watchdog timer. B0MOV WDTR, A … … CALL SUB1 CALL SUB2 … … MAIN Version 1.7 SONiX TECHNOLOGY CO., LTD Page 67...
  • Page 68 ; I/O and RAM are correct. Clear watchdog timer and ; execute program. B0BSET FWDRST ; Only one clearing watchdog timer of whole program. … CALL SUB1 CALL SUB2 … … … MAIN Version 1.7 SONiX TECHNOLOGY CO., LTD Page 68...

  • Page 69: Timer 0 (T0)

    Bit 2 TC0X8: TC0 internal clock source control bit. 0 = TC0 internal clock source is Fcpu. TC0RATE is from Fcpu/2~Fcpu/256. 1 = TC0 internal clock source is Fosc. TC0RATE is from Fosc/1~Fosc/128. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 69...
  • Page 70 T0ENB: T0 counter control bit. 0 = Disable T0 timer. 1 = Enable T0 timer.  Note: In RTC mode, the T0 interval time is fixed at 0.5 sec and T0C is 256 counts. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 70...

  • Page 71: T0C Counting Register

    488.281 us Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us  Note: In RTC mode, T0C is 256 counts and generatesT0 0.5 sec interval time. Don’t change T0C value in RTC mode. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 71...

  • Page 72: T0 Timer Operation Sequence (High_Clk = Ihrc)

    Set T0 interrupt interval time. A,#7FH B0MOV T0C,A ; Set T0C value.  Set T0 timer function mode. B0BSET FT0IEN ; Enable T0 interrupt function.  Enable T0 timer. B0BSET FT0ENB ; Enable T0 timer. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 72...

  • Page 73: Rtc Operation Sequence (High_Clk ="Ihrc_Rtc" And "T0Tb = 1")

    CKT_T0CVAL sub-routing (Check T0C value status). CKT_T0CVAL: A, T0C ; Read T0C value NEWT0C, A ; Save to NEWT0C A, OLDT0C ; A sub OLDT0C value. B0BTS0 ; If FC = 0, borrow Version 1.7 SONiX TECHNOLOGY CO., LTD Page 73...
  • Page 74 ; Call delay time = over 1/32.768ms (for RTC limit). T0FLAG ; Clear T0FLAG. B0BCLR FT0IRQ ; Clear FT0IRQ. A, T0C OLDT0C, A ; Update T0C value CALL UPDATE_TIME ; Update time. CKT_OTHER: Version 1.7 SONiX TECHNOLOGY CO., LTD Page 74...

  • Page 75: Timer/Counter 0 (Tc0)

    TC0 Rate TC0R Reload ALOAD0, TC0OUT (Fcpu/2~Fcpu/256) Data Buffer TC0X8 PWM0OUT Fcpu Compare TC0CKS TC0ENB Load Fosc TC0C 8-Bit Binary Up TC0 Time Out Counting Counter TC0 Rate (Fosc/1~Fosc/128) CPUM0,1 INT0 (Schmitter Trigger) Version 1.7 SONiX TECHNOLOGY CO., LTD Page 75...

  • Page 76: Tc0M Mode Register

    1 = Enable TC0 timer.  Note: When TC0CKS=1, TC0 became an external event counter and TC0RATE is useless. No more P0.0 interrupt request will be raised. (P0.0IRQ will be always 0). Version 1.7 SONiX TECHNOLOGY CO., LTD Page 76...

  • Page 77: Tc0X8, Tc0Gn Flags

    111 = fcpu/2. Bit 7 T0ENB: T0 counter control bit. 0 = Disable T0 timer. 1 = Enable T0 timer.  Note: Under TC0 event counter mode (TC0CKS=1), TC0X8 bit and TC0RATE are useless. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 77...

  • Page 78: Tc0C Counting Register

    16 us 1000 ms 3906.25 us Fosc/64 2.048 ms 8 us 500 ms 1953.125 us Fosc/32 1.024 ms 4 us 250 ms 976.563 us Fosc/16 0.512 ms 2 us 125 ms 488.281 us Version 1.7 SONiX TECHNOLOGY CO., LTD Page 78...
  • Page 79 1 us 62.5 ms 244.141 us Fosc/4 0.128 ms 0.5 us 31.25 ms 122.07 us Fosc/2 0.064 ms 0.25 us 15.625 ms 61.035 us Fosc/1 0.032 ms 0.125 us 7.813 ms 30.517us Version 1.7 SONiX TECHNOLOGY CO., LTD Page 79...

  • Page 80: Tc0R Auto-Load Register

    TC0R initial value = N - (TC0 interrupt interval time * input clock) = 256 - (10ms * 8MHz / 8 / 64) = 256 - (10 * 8 * 10 / 8 / 64) = 100 = 64H Version 1.7 SONiX TECHNOLOGY CO., LTD Page 80...

  • Page 81: Tc0 Clock Frequency Output (Buzzer)

    ; Enable TC0 output to P1.1 and disable P1.1 I/O function B0BSET FALOAD0 ; Enable TC0 auto-reload function B0BSET FTC0ENB ; Enable TC0 timer  Note: Buzzer output is enable, and “PWM0OUT” must be “0”. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 81...

  • Page 82: Tc0 Timer Operation Sequence

    B0BSET FTC0OUT ; Enable TC0OUT (Buzzer) function. B0BSET FPWM0OUT ; Enable PWM function. B0BSET FTC0GN ; Enable TC0 green mode wake-up function.  Enable TC0 timer. B0BSET FTC0ENB ; Enable TC0 timer. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 82...

  • Page 83: Pwm0 Mode

    31.25K Overflow per 256 count The Output duty of PWM is with different TC0R. Duty range is from 0/256~255/256. …… …… …… …… TC0 Clock TC0R=00H High TC0R=01H High TC0R=80H High TC0R=FFH Version 1.7 SONiX TECHNOLOGY CO., LTD Page 83...

  • Page 84: Tc0Irq And Pwm Duty

    INCMS BUF0 ; Get the new TC0R value from the BUF0 buffer defined by ; programming. B0MOV A, BUF0 B0MOV TC0R, A   Note: The PWM can work with interrupt request. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 84...

  • Page 85: Pwm0 Duty Changing Notice

    Above diagram is shown the waveform with fixed TC0R. In every TC0C overflow PWM output “High, when TC0C≧TC0R PWM output ”Low”.   Note: Setting PWM duty in program processing must be at the new cycle start. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 85...

  • Page 86: Uart

    The UART interface is an universal asynchronous receiver/transmitter method. The serial interface is applied to low speed data transfer and communicate with low speed peripheral devices. The UART transceiver of Sonix 8-bit MCU allows RS232 standard and supports one byte data length. The transfer format has start bit, 8-bit data, parity bit and stop bit.

  • Page 87: Uart Transfer Format

    The stop bit is like start bit using a simple format to indicate the end of UART transfer. The stop bit format is low to high edge change and the duration is one bit period. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 87...

  • Page 88: Abnormal Pocket

    UART Main Clock Rate Fuart (Fhosc=8Hz) Selection, URS[2:0] 000b Fhosc/1 8MHz 001b Fhosc/2 4MHz 010b Fhosc/4 2MHz 011b Fhosc/8 1MHz 100b Fhosc/16 0.5MHz 101b Fhosc/32 0.25MHz 110b Fhosc/64 0.125MHz 111b Fhosc/128 0.625MHz Version 1.7 SONiX TECHNOLOGY CO., LTD Page 88...
  • Page 89 57600 Fhosc/1 000b 57971 0.64% 102400 Fhosc/1 000b 102564 0.16% 115200 Fhosc/1 000b 114286 -0.79%  Note: We strongly recommend not to set URCR = 0xFF, or UART operation would be error. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 89...

  • Page 90: Uart Receiver Control Register

    0 = Disable UART TX. UTX pin is GPIO mode or returns to GPIO status. 1 = Enable UART TX. UTX pin exchanges from GPIO mode to UART TX mode and idle high status. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 90...

  • Page 91: Uart Transmitter Control Register

    Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 URXD URXD7 URXD6 URXD5 URXD4 URXD3 URXD2 URXD1 URXD0 Read After Reset Bit [7:0] URXD: UART received data buffer. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 91...

  • Page 92: Uart Operation Examlpe

    ; Check TX operation. B0BTS0 FUTXBZ ; Check UTXBZ bit. CHKTX ; UTXBZ=1, TX is operating. ENDTX ; UTXBZ=0, the end of TX.  Note: UART TX operation is started through loading UTXD data buffer. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 92...

  • Page 93: Buzzer Function

    01 = 1.96 KHz. 10 = 3.9 KHz. 11 = 7.8 KHz. Bit 2 BZRENB: Buzzer output control bit. 0 : P03 as GPIO Mode. 1 : P03 as Buzzer Mode. Output Buzzer signal Version 1.7 SONiX TECHNOLOGY CO., LTD Page 93...

  • Page 94: Lcd Driver

    11.1 OVERVIEW LCD driver includes R-type and C-type structures with 4 common pins and 16 segment pins in the SN8P2977. The LCD scan timing is 1/4 duty with 1/2 bias or 1/3 bias structure, all support in R-type and C-type mode to yield 64 dots LCD driver.
  • Page 95 2/3*VLCD COM0 1/3*VLCD VLCD 2/3*VLCD COM1 1/3*VLCD VLCD 2/3*VLCD COM2 1/3*VLCD VLCD 2/3*VLCD COM3 1/3*VLCD VLCD 2/3*VLCD SEG0 (1010b) 1/3*VLCD VLCD 2/3*VLCD SEG0 (0101b) 1/3*VLCD LCD Drive Waveform, 1/4 duty, 1/3 bias Version 1.7 SONiX TECHNOLOGY CO., LTD Page 95...

  • Page 96: Lcdm1 Register

    1.40V 2.8V 0.96V 1.93V 2.9V 1.45V 1.45V 2.9V 1.00V 2.00V 3.0V 1.50V 1.50V 3.0V 1.03V 2.06V 3.1V 1.55V 1.55V 3.1V 1.06V 2.13V 3.2V 1.60V 1.60V 3.2V 1.10V 2.20V 3.3V 1.65V 1.65V 3.3V Version 1.7 SONiX TECHNOLOGY CO., LTD Page 96...
  • Page 97 In R-Type Mode, Power saving level III > II > I > Disable.  Note_1: Macro “RomwrtVpp” instruction cover procedures of internal VPP generation and ROMWRT instruction for ISP function without external 7.5V requirement. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 97...

  • Page 98: C-Type Lcd Driver Mode

    1/3 and 1/2 Basic C-type LCD Application Circuit  Note1: In C-type mode, a 1uF capacitor is connected to pin VLCD to VSS.  Note2: VLCD output voltage can be set from 2.6V to 3.3V and with ±0.2V accuracy. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 98...

  • Page 99: R-Type Lcd Driver Mode

    The following diagram shows the connection of 1/4 duty with 1/3 bias and 1/2 bias. 1/4 duty with 1/3 bias: SN8P2977 35 k Ω 35 k Ω LCDBIAS = 0 ( Open ) 35 k Ω LCDMOD [1:0] VLCD R-Type LCD current consumption =  Version 1.7 SONiX TECHNOLOGY CO., LTD Page 99...
  • Page 100 LCD current consumption =   Note_1: In R-Type LCD driver mode, VLCD power is auto connected to VDD via internal circuit. Pin VLCD do not connect to any power source.  Version 1.7 SONiX TECHNOLOGY CO., LTD Page 100...

  • Page 101: Lcd Ram Location

    FLCDMOD1 B0BSET FLCDENB ; Enable LCD driver. C-Type LCD Setting: B0BCLR FLCDMOD0 ; C-Type LCD. B0BCLR FLCDMOD1 Delay 5ms ; Delay time for CP-VLCD output stable. B0BSET FLCDENB ; Enable LCD driver. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 101...

  • Page 102: In System Program Rom

    Bit 2 Bit 1 Bit 0 ROMDAL ROMDA7 ROMDA6 ROMDA5 ROMDA4 ROMDA3 ROMDA2 ROMDA1 ROMDA0 Read/Write After reset ROMDA[15:0] : ISP ROM Programming Data ROM Data which want to Programming into ROM area.. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 102...

  • Page 103: Isp Rom Routine Example

    ; Disable Interrupt. RomwrtVpp ; ISP ROM Write Macro Instruction B0BSET FGIE ; Enable Interrupt if necessary. Incms ROMADRL ;ISP Address increase incms ROMADRH decms ISP_Cnt ;Data counter ISP_End: End of ISP Version 1.7 SONiX TECHNOLOGY CO., LTD Page 103...

  • Page 104: Regulator, Pgia And Adc

    Regulator, PGIA and ADC 13.1 OVERVIEW The SN8P2977 has a built-in Voltage Regulator to support a stable voltage 2.4V/2.8V/3.2V from pin AVDDR and 0.75V/1.0V/1.5V/2.0V from pin AVE+ with maximum 10mA current driving capacity. The AVDDR provides stable voltage for internal circuits (PGIA, ADC) and external sensor (load cell or thermistor).

  • Page 105: Voltage Regulator

    8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC 13.3 Voltage Regulator SN8P2977 is built in voltage regulators, which can provide a stable 2.4V/2.8V/3.2V (pin AVDDR) and 0.75V/1.0V1.5V/2.0V (pin AVE+) with maximum 10mA current driving capacity. Register VREG can enable or disable AVDDR and AVE output voltage.

  • Page 106: Pgia -Programmable Gain Instrumentation Amplifier

    8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC 13.4 PGIA -Programmable Gain Instrumentation Amplifier SN8P2977 includes a low noise chopper-stabilized programmable gain instrumentation amplifier (PGIA) with selection gains of 1x, 4x, 8x, 16x, 32x, 64x, 128x and 200x controlled by register AMPM1. The PGIA also provides two multiplexers.
  • Page 107 Note_4: When CHS[7:0]=01100110 (Temperature detection mode) or CHS[7:0]=01010101 (VDD detection mode), PGIA Gain always set 1x (GS0[2:0]=000) application, the AI+/AI- signal will bypass PGIA and input ADC directly. PGIA can be disabled (AMPENB=0) for power saving. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 107...

  • Page 108: Ampm- Amplifier Mode Control Register

    (AMPENB=0) for power saving.  Note_2: When PGIA Gain set 1x (GS[2:0]=000) application, the AI+/AI- signal input buffer of PGIA must be enabled (AMPENB=1) for input high impedance characteristic of ADC. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 108...

  • Page 109: Temperature Sensor (Ts)

    13.5 Temperature Sensor (TS) In applications, sensor characteristic might change in different temperature also. To get the temperature information, SN8P2977 build in a temperature senor (TS) for temperature measurement. Select the respective PGIA channel to access the Temperature Sensor ADC output.
  • Page 110 ; PGIA chopper Enable, Gain= 1x B0MOV AMPM, A ; PGIA chopper Freq. 31.25kHz. B0BCLR AMPENB ; Select VDD Voltage Detect function. … ; V (X+, X-) Output = 1/8*VDD x 1 … Version 1.7 SONiX TECHNOLOGY CO., LTD Page 110...

  • Page 111: 24-Bit Analog To Digital Converter (Adc)

    13.6 24-Bit Analog to Digital Converter (ADC) The SN8P2977 integrated a 24-bit ΔΣ Analog-to-Digital Converters (ADC) with decimation filters can be set for variable throughputs range from 7.6 Hz up to 5.2 kHz. A reference voltage (Vref) is built in internal with selective range from 0.36V to 1.2V in AVDDR=2.4V condition, or an external reference voltage can be used to adjust an adequate range via...

  • Page 112: Adc Gain And Offset

      Offset 524287 -524288 20bits: Vref 0, -1/4, -1/2 or -3/4 x Vref offset PGIA: 1x ~ 200x ADC_Gain: 1x and 2x Vref Source: Internal Vref Vref Range: 0.225V ~ 1.6V Version 1.7 SONiX TECHNOLOGY CO., LTD Page 112...

  • Page 113: Output Word Rate

     Note_1: The Operation range of ADC Reference Voltage (Vref) is from 0.36V to 1.2V@AVDDR=2.4V.  Note_2: In Temperature detection mode(CHS=0x66) ,The Operation range of ADC Reference Voltage (Vref) is from VBG*2/3= 0.8V (IRVS=10xx). Version 1.7 SONiX TECHNOLOGY CO., LTD Page 113...

  • Page 114: Adcm2- Adc Mode2 Register

    ADC output data is dummy after 15us later of ADC enable. The 2 ADC output data is unstable data after 1/WR later of 1 ADC data. The 3 … are stable data after 1/WR later of each. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 114...

  • Page 115: Adc Data Register

    Note 5: The Negative Full-Scale-Output value of ADC conversion is 0x80000H.  Note 6: Because of the ADC design limitation, the ADC Linear range is +29491 ~ -29491 (16-bit). (+0.9*Vref ~ - 0.9*Vref). The MAX ADC output must keep inside this range. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 115...
  • Page 116 8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC Following table shows the Noise and ENOB (RMS and peak-to-peak) of the SN8P2977 ADC with different output word rate rates and gain settings. These numbers are typical and are generated using a differential input-short condition, ADC Vref 0.84V and 1024-data of measurement.
  • Page 117  Note 1: Please set ADC relative registers first, than enable ADC function bit.  Note 2: Before enable ADC function, please set analog function (regulators, PGIA and ADC) and wait 300us for all functions stable. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 117...
  • Page 118 A, ADCDH B0MOV Data_H_Buf, A ; Move ADC conversion High byte to Data Buffer B0MOV A, ADCDM B0MOV Data_M_Buf, A ; Move ADC conversion Medium byte to Data Buffer … … … Version 1.7 SONiX TECHNOLOGY CO., LTD Page 118...
  • Page 119 ; Disable PGIA function. B0BCLR FADCENB ; Disable ADC function. B0BCLR FAVDDRENB ; Disable AVDDR. B0BCLR FLCDENB ; Disable LCD display. B0BCLR FBGRENB ; Disable Band Gap Voltage. GreenMode ; System into Green mode. (Macro) Version 1.7 SONiX TECHNOLOGY CO., LTD Page 119...
  • Page 120  Note 4: The second ADC will available after ADC channel switched and in condition of ADC not disable status.  Note 5: For increasing fast ADC conversion accuracy, recommend averaging several times of ADC row Data for application. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 120...

  • Page 121: Lbtm: Low Battery Detect

    13.7 LBTM: Low Battery Detect SN8P2977 provided two different ways to measure VDD Voltage. One is from ADC reference voltage selection. It will be more precise but take more time and a little bit complex. Another way is using build in Voltage Comparator via internal or external input path to detect VDD voltage level.
  • Page 122  Note_3: After getting LBTO data,Please set LBTENB = 0 to disable LBT Low Battery Detect function.  Note_4: LBT external input P10 and P11IO function is not available in ICE emulation.  Note_5: IO input voltage must keep lower than VDD.  Version 1.7 SONiX TECHNOLOGY CO., LTD Page 122...

  • Page 123: Analog Setting And Application

    8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC 13.8 Analog Setting and Application The most applications of SN8P2977 were for DC measurement ex. Weight scale, Pressure measure. Following table indicate different applications setting which MCU power source came from CR2032 battery, AA/AAA dry battery or external Regulator.
  • Page 124 Note_3: When MCU VDD power sources from AA/AAA dry battery directly, not via other LDO, 1uf capacitor can be applied to VDD and without VDD drop when regulator turns on at low battery status. Version 1.7 SONiX TECHNOLOGY CO., LTD Page 124...

  • Page 125: Application Circuit

    AVSS TX / P04 0.1 uf VBAT AVDD AVDDR Key 1 Key 2 ON/OFF Load Cell 0.1uf  Note : DVDD/AVDD capacitors should be as close as possible with pins of IC Version 1.7 SONiX TECHNOLOGY CO., LTD Page 125...

  • Page 126: Thermometer Application Circuit

    TX / P04 0.1 uf VBAT AVDD Key 1 Key 2 ON/OFF Thermopile 0.1uf AVDDR Thermistor 0.1uf  Note : DVDD/AVDD capacitors should be as close as possible with pins of IC Version 1.7 SONiX TECHNOLOGY CO., LTD Page 126...

  • Page 127: Instruction Set Table

    The “M” is memory including system registers and user defined memory. Note: 2. If M is system register, the "N" is zero, or the "N" = 1. Note: 3. If the branch condition is true, the "S=1", or the "S=0". Version 1.7 SONiX TECHNOLOGY CO., LTD Page 127...

  • Page 128: Development Tools

     Note: MPIII Writer doesn’t support SN8P2977 OTP programming. IDE (Integrated Development Environment) 16.1.3 SONiX 8-bit MCU integrated development environment include Assembler, ICE debugger and OTP writer software.  SN8ICE 2K Plus II  Easy Writer, MP-Easy and MPIII Writer doesn’t support SN8P2977 Version 1.7...

  • Page 129: Otp Programming Pin To Transition Board Mapping

    ALSB/PDB P0.4 SN8P2977 Package Type Programming with 48 PIN adapter board and with transition board socket: 48 PIN adapter board connect to MP PRO Writer. Plug in the transition board socket, MP251 or MP252 or MP253, on the adapter board (J1/J2).

  • Page 130: Appendix A: Ev-Kit Board Circuit

    SN8P2977 8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC 16.3 APPENDIX A: EV-KIT BOARD CIRCUIT Version 1.7 SONiX TECHNOLOGY CO., LTD Page 130...

  • Page 131: Sn8P2977 Emulation

    Sonix provides a complete EV-KIT for SN8P2977 emulation, which includes an ICE SN8ICE2K_Plus_II, a SN8P2977 EV Board, Sonix Assembler and Complier. Users are able to do the programming on the computer and to simulate the program code using the software or the ICE itself. On the other hand, when executing the program and monitoring the RAM status, users can user various functions such as Breakpoint, Single step etc.

  • Page 132: Sn8P2977 Ev Board Description

    SN8P2977 8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC 16.4.3 SN8P2977 EV Board DESCRIPTION Sonix provides SN8P2977 EV board for all functions emulation shown in FIG.1 FIG.1 SN8P2977 EV board Version 1.7 SONiX TECHNOLOGY CO., LTD Page 132...

  • Page 133: Ev Board Setting

    Notice for EV Emulation 1. ICE VDD must switch to 3.3V. VDD 5V is not available for SN8P2977 EV-Kit 2. SW3 must switch to “ICE” position. 3. Low Battery Detect (LBT) function only supports internal LBT emulation not support P11 Input.

  • Page 134: Electrical Characteristic

    Sleep Mode Idd11 Vdd= 3V LVD detect level Internal POR detect level Internal High RC Oscillator Frequency Internal High Clock Freq. 8-1.5% 8+1.5% MHz IHRC ( Vdd = 2.4V ~ 3.6V, Temperature: 25℃) Version 1.7 SONiX TECHNOLOGY CO., LTD Page 134...
  • Page 135 VDD: 2.4~3.6V. Temp.: -10 ~ 50 ℃ LBT Driver Condition: V =3.6V Internal Low-Battery detect voltage Condition: V =3.0V ILBT Condition: V =2.4V 2.25 2.55 External Low-Battery detect voltage Condition: VDD =2.2~3.6V, P10 input comparator ELBT Version 1.7 SONiX TECHNOLOGY CO., LTD Page 135...

  • Page 136: Package Information

    2.550 60.960 62.230 64.770 0.600 15.240 0.540 0.545 0.550 13.716 13.843 13.970 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.630 0.650 0.067 16.002 16.510 1.702 θ° 0° 7° 15° 0° 7° 15° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 136...

  • Page 137: Ssop 48 Pin

    15.748 15.875 16.002 0.291 0.295 0.299 7.391 7.493 7.595 0.025 0.635 0.396 0.406 0.416 10.058 10.312 10.566 0.020 0.030 0.040 0.508 0.762 1.016 0.056 1.422 0.003 0.076 θ° 0° 8° 0° 8° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 137...

  • Page 138: Lqfp 48 Pin

    8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC 18.3 LQFP 48 PIN SYMBOLS (mm) 0.05 0.15 1.35 1.45 0.09 0.16 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.5 BSC 0.17 0.27 0.45 0.75 1 REF Version 1.7 SONiX TECHNOLOGY CO., LTD Page 138...

  • Page 139: Qfn 32 Pin

    0.157 BSC 4.00 BSC 0.016 BSC 0.40 BSC 0.014 0.016 0.018 0.35 0.40 0.45 0.013 0.015 0.017 0.332 0.382 0.432 0.008 0.20 0.102 0.106 0.108 2.60 2.70 0.102 0.106 0.108 2.60 2.70 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 139...

  • Page 140: Tssop28 Pin

    0.026 BSC 0.65 BSC 0.018 0.024 0.030 0.45 0.60 0.75 0.039 REF 1.00 REF 0.008 0.20 θ ° 0° 8° 0° 8° 0.004 0.10 0.094 0.124 2.40 3.15 0.174 0.219 4.41 5.56 Version 1.7 SONiX TECHNOLOGY CO., LTD Page 140...

  • Page 141: Ssop20 Pin

    3.900 4.000 0.025 0.635 0.010 0.017 0.020 0.250 0.420 0.500 0.016 0.025 0.050 0.400 0.635 1.270 0.039 0.041 0.043 1.000 1.050 1.100 0.059 1.500 0.004 0.100 θ ° 0° 8° 0° 8° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 141...

  • Page 142: Sop 18 Pin

    0.305 0.447 0.455 0.463 11.354 11.557 11.760 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.325 10.643 0.016 0.033 0.050 0.406 0.838 1.270 θ° 0° 4° 8° 0° 4° 8° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 142...

  • Page 143: Sop 16 Pin

    0.049 1.25 0.012 0.020 0.31 0.51 0.004 0.010 0.10 0.25 0.39BSC 9.90BSC 0.236BSC 6.00BSC 0.154BSC 3.90BSC 0.05BSC 1.27BSC 0.016 0.050 0.40 1.27 0.010 0.020 0.25 0.50 θ ° 0° 8° 0° 8° Version 1.7 SONiX TECHNOLOGY CO., LTD Page 143...

  • Page 144: Marking Definition

    Marking Definition 19.1 INTRODUCTION There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit MCU for order or obtains information. This definition is only for Blank OTP MCU. 19.2 MARKING INDETIFICATION SYSTEM SN8 X Part No .

  • Page 145: Marking Example

    ..9=09 A=10 B=11 ..1=January Month 2=February ..9=September A=October B=November C=December 03= 2003 Year 04= 2004 05= 2005 06= 2006 ..Version 1.7 SONiX TECHNOLOGY CO., LTD Page 145...
  • Page 146 SONIX product could create a situation where personal injury or death may occur.

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