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SN8P2743 Series
USER'S MANUAL
Version 2.0
SN8P2743
SN8P2742
SN8P27411
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
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ADC, OP-amp, Comparator 8-Bit Micro-Controller
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SN8P2740 Series
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Version 2.0
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Table of Contents
Related Manuals for SONIX SN8P2743 Series
Summary of Contents for SONIX SN8P2743 Series
- Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.
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Page 2: Amendent History
2. Modify “ANALOG COMPARATOR 0~2” chapters description and others. Add “To support MUL / DAA instruction” description. VER 1.9 Jul. 2015 VER 2.0 Mar. 2016 Modify operating temperature from 0~70℃ to -20~70℃ and others. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 2... -
Page 3: Table Of Contents
External Reset IC ..............................43 SYSTEM CLOCK ................................... 44 OVERVIEW ..................................44 (INSTRUCTION CYCLE) ............................. 44 SYSTEM HIGH-SPEED CLOCK ........................... 44 4.3.1 HIGH_CLK CODE OPTION ..........................45 4.3.2 INTERNAL HIGH-SPEED OSCILLATOR RC TYPE (IHRC) ................45 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 3... - Page 4 NORMAL COMPARATOR MODE ..........................90 COMPARATOR 0 SPECIAL FUCNITON ........................92 COMPARATOR MODE REGISTER ..........................93 COMPARATOR APPLICATION NOTICE ........................93 COMPARATOR 0 OPERATION EXPLAME ........................ 94 ANALOG COMPARAOTR 1 ............................95 10.1 OVERVIEW ..................................95 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 4...
- Page 5 SK-DIP 24 PIN ................................130 20.2 SOP 24 PIN ..................................131 20.3 P-DIP 20 PIN ................................. 132 20.4 SOP 20 PIN ..................................133 20.5 P-DIP 16 PIN ................................. 134 20.6 SOP 16 PIN ..................................135 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 5...
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Page 6: Product Overview
Features Selection Table Timer Pulse Ext. Comp- CHIP Stack Buzzer Package Generator arator SKDIP24 SN8P2743 4K*16 128*8 8-ch SOP24 PDIP20 SN8P2742 4K*16 128*8 6-ch SOP20 PDIP16 SN8P27411 4K*16 128*8 6-ch SOP16 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 6... -
Page 7: System Block Diagram
P1.0/OPN P1.4/CM2P P1.1/OPP P1.3/CM2N P1.2/OPO SN8P2742P (DIP 20 pin) SN8P2742S (SOP 20 pin) XIN/P0.6 P4.5/AIN5 XOUT/P0.5/BZ P4.4/AIN4 RST/VPP/P0.4/ P0.1/PWM0 P4.3/AIN3/CM0O P0.2/CM0P P4.2/AIN2/CM1O P0.3/CM0N P4.1/AIN1/CM2O P1.6/CM1P P4.0/AIN0/AVREFH P1.5/CM1N P1.0/OPN P1.4/CM2P P1.1/OPP P1.3/CM2N P1.2/OPO Version 2.0 SONiX TECHNOLOGY CO., LTD Page 7... -
Page 8: Pin Descriptions
Level change wake-up. OPP: The positive input pin of OP amp. P1.2: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change wake-up. P1.2/OPO OPO: The output pin of OP amp. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 8... -
Page 9: Pin Circuit Diagrams
Ext. Reset Code Option I/O Input Bus Reset Oscillator shared pin structure: Pull-Up Resistor High_Clk PnUR Code Option I/O Input Bus Output I/O Output Bus Latch Oscillator Driver GPIO structure: Version 2.0 SONiX TECHNOLOGY CO., LTD Page 9... - Page 10 SN8P2740 Series ADC, OP-amp, Comparator 8-Bit Micro-Controller Pull-Up Resistor PnUR I/O Input Bus Output I/O Output Bus Latch P0.1: Open-drain shared pin, output only I/O: OUTSIDE INSIDE Open-Drain I/O Bus Control Version 2.0 SONiX TECHNOLOGY CO., LTD Page 10...
- Page 11 PnUR CMnEN I/O Input Bus Output I/O Output Bus CMnREF Latch Comparator Positive Input Comparator Output Pin: Pull-Up Resistor PnUR CMnEN I/O Input Bus Output I/O Output Bus CMnOEN Latch Comparator Output Version 2.0 SONiX TECHNOLOGY CO., LTD Page 11...
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Page 12: Central Processor Unit (Cpu)
The Interrupt vector is the head of interrupt service routine when any interrupt occurring. The General purpose area is main program area including main loop, sub-routines and data table. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 12... -
Page 13: Reset Vector (0000H)
Example: Defining Reset Vector ; 0000H START ; Jump to user program address. … START: ; 0010H, The head of user program. … ; User program … ENDP ; End of program Version 2.0 SONiX TECHNOLOGY CO., LTD Page 13... -
Page 14: Interrupt Vector (0008H)
RETI ; End of interrupt service routine … START: ; The head of user program. … ; User program … START ; End of user program … ENDP ; End of program Version 2.0 SONiX TECHNOLOGY CO., LTD Page 14... - Page 15 ; End of program. Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
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Page 16: Look-Up Table Description
Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Example: INC_YZ macro. INC_YZ MACRO INCMS ; Z+1 ; Not overflow INCMS ; Y+1 ; Not overflow ENDM Version 2.0 SONiX TECHNOLOGY CO., LTD Page 16... - Page 17 ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 … TABLE1: 0035H ; To define a word (16 bits) data. 5105H 2012H … Version 2.0 SONiX TECHNOLOGY CO., LTD Page 17...
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Page 18: Jump Table Description
; ACC = 3, jump to A3POINT SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size. - Page 19 ; ACC = 1, jump to A1POINT 0X0102 A2POINT ; ACC = 2, jump to A2POINT 0X0103 A3POINT ; ACC = 3, jump to A3POINT 0X0104 A4POINT ; ACC = 4, jump to A4POINT Version 2.0 SONiX TECHNOLOGY CO., LTD Page 19...
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Page 20: Checksum Calculation
; If Not jump to checksum calculate CHECKSUM_END ; If Yes checksum calculated is done. Y_ADD_1: INCMS ; Increase Y ; Jump to checksum calculate CHECKSUM_END: … … END_USER_CODE: ; Label of program end Version 2.0 SONiX TECHNOLOGY CO., LTD Page 20... -
Page 21: Data Memory (Ram)
“ 0FFh End of Bank 0 The 128-byte general purpose RAM is in Bank 0. Sonix provides “Bank 0” type instructions (e.g. b0mov, b0add, b0bts1, b0bset…) to control Bank 0 RAM in non-zero RAM bank condition directly. 2.2.1 SYSTEM REGISTER 2.2.1.1... -
Page 22: Bit Definition Of System Register
0FAH S2PC7 S2PC6 S2PC5 S2PC4 S2PC3 S2PC2 S2PC1 S2PC0 STK2L 0FBH S2PC11 S2PC10 S2PC9 S2PC8 STK2H 0FCH S1PC7 S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 STK1L 0FDH S1PC11 S1PC10 S1PC9 S1PC8 STK1H Version 2.0 SONiX TECHNOLOGY CO., LTD Page 22... - Page 23 2. All of register names had been declared in SN8ASM assembler. 3. One-bit name had been declared in SN8ASM assembler with “F” prefix code. 4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 23...
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Page 24: Accumulator
“PUSH”, “POP” save and load ACC, PFLAG data into buffers. Example: Protect ACC and working registers. INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector Version 2.0 SONiX TECHNOLOGY CO., LTD Page 24... -
Page 25: Program Flag
1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero. Note: Refer to instruction set table for detailed information of C, DC and Z flags. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 25... -
Page 26: Program Counter
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. CMPRS A, #12H ; To skip, if ACC = 12H. C0STEP ; Else jump to C0STEP. … … C0STEP: Version 2.0 SONiX TECHNOLOGY CO., LTD Page 26... - Page 27 DECS BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: DECMS instruction: DECMS BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: Version 2.0 SONiX TECHNOLOGY CO., LTD Page 27...
- Page 28 ; If ACC = 0, jump to A0POINT A1POINT ; ACC = 1, jump to A1POINT A2POINT ; ACC = 2, jump to A2POINT A3POINT ; ACC = 3, jump to A3POINT … … Version 2.0 SONiX TECHNOLOGY CO., LTD Page 28...
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Page 29: H, L Registers
; Clear @HL to be zero ; L – 1, if L = 0, finish the routine DECMS CLR_HL_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … … Version 2.0 SONiX TECHNOLOGY CO., LTD Page 29... -
Page 30: Y, Z Registers
Bit 2 Bit 1 Bit 0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Read/Write After reset Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 30... -
Page 31: Addressing Mode
; To clear Y register to access RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 31... -
Page 32: Stack Operation
STKP = 5 STK5H STK5L STKP STKP STKP = 4 STK4H STK4L STKP = 3 STK3H STK3L STKP = 2 STK2H STK2L STKP = 1 STK1H STK1L STKP = 0 STK0H STK0L Version 2.0 SONiX TECHNOLOGY CO., LTD Page 32... -
Page 33: Stack Registers
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKnL SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0 Read/Write After reset STKn = STKnH , STKnL (n = 7 ~ 0) Version 2.0 SONiX TECHNOLOGY CO., LTD Page 33... -
Page 34: Stack Operation Example
STKP Register Stack Buffer Stack Level Description STKPB2 STKPB1 STKPB0 High Byte Low Byte STK7H STK7L STK6H STK6L STK5H STK5L STK4H STK4L STK3H STK3L STK2H STK2L STK1H STK1L STK0H STK0L Free Free Version 2.0 SONiX TECHNOLOGY CO., LTD Page 34... -
Page 35: Code Option Table
P04: Set reset pin to general input only pin (P0.4). The external reset function is disabled and the pin is input pin. 2.5.3 Security code option Security code option is OTP ROM protection. When enable security code option, the ROM code is secured and not dumped complete ROM contents. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 35... -
Page 36: Reset
High Detect Low Detect Watchdog Overflow Watchdog Normal Run Watchdog Reset Watchdog Stop System Normal Run System Status System Stop Power On External Watchdog Delay Time Reset Delay Reset Delay Time Time Version 2.0 SONiX TECHNOLOGY CO., LTD Page 36... -
Page 37: Power On Reset
(e.g. EFT interference or external loading changed). The brown out reset would make the system not work well or executing program error. System Work Well Area System Work Error Area Brown Out Reset Diagram Version 2.0 SONiX TECHNOLOGY CO., LTD Page 37... -
Page 38: The System Operating Voltage
The dead-band definition is the system minimum operating voltage above the system reset voltage. 3.6 LOW VOLTAGE DETECTOR (LVD) LVD Detect Voltage Power Power is below LVD Detect Voltage and System Reset. System Normal Run System Status System Stop Power On Delay Time Version 2.0 SONiX TECHNOLOGY CO., LTD Page 38... - Page 39 ADC, OP-amp, Comparator 8-Bit Micro-Controller The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by each MCU.
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Page 40: Brown Out Reset Improvement
IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead-band. The external reset information is described in the next section. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 40... -
Page 41: External Reset
The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference. Note: The reset circuit is no any protection against unusual power or brown out reset. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 41... -
Page 42: Diode & Rc Reset Circuit
PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener specification. Select the right zener voltage to conform the application. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 42... -
Page 43: Voltage Bias Reset Circuit
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can improve all power variation. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 43... -
Page 44: System Clock
4.3 SYSTEM HIGH-SPEED CLOCK The system high-speed clock has internal and external two-type. The external high-speed clock includes 4MHz, 12MHz, 32KHz crystal/ceramic and RC type. These high-speed oscillators are selected by “High_CLK” code option. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 44... -
Page 45: High_Clk Code Option
ADC, OP-amp, Comparator 8-Bit Micro-Controller 4.3.1 HIGH_CLK CODE OPTION For difference clock functions, Sonix provides multi-type system high clock options controlled by “High_CLK” code option. The High_CLK code option defines the system oscillator types including IHRC_16M, RC, 32K X‟tal, 12M X‟tal and 4M X‟tal. -
Page 46: System Low-Speed Clock
; oscillator called power down mode (sleep mode). Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1 (32K, watchdog disable) bits of OSCM register. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 46... -
Page 47: Oscm Register
; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P0.0 ; Measure the Fcpu frequency by oscilloscope. Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC frequency. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 47... -
Page 48: System Clock Timing
External Reset Pin Reset Timing Reset pin falling edge trigger system reset. External Reset Pin Reset pin returns to high status. External Reset Flag Oscillator Tcfg Tost Tosp Fcpu (Instruction Cycle) System is under reset status. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 48... - Page 49 Green Mode Wake-up Timing Edge trigger system wake-up. Wake-up Pin Falling Edge Wake-up Pin Rising Edge Timer overflow. Timer 0xFD 0xFE 0xFF 0x00 0x01 0x02 Oscillator Fcpu (Instruction Cycle) System inserts into green mode. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 49...
- Page 50 The RC type oscillator‟s start-up time is faster than crystal type oscillator. RC Oscillator Tost Ceramic/Resonator Tost Crystal Tost Low Speed Crystal (32K, 455K) Tost Version 2.0 SONiX TECHNOLOGY CO., LTD Page 50...
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Page 51: System Operation Mode
All active All inactive Wakeup source P0, P1, T0 Reset P0, P1 Reset EHOSC: External high-speed oscillator (XIN/XOUT). IHRC: Internal high-speed oscillator RC type. ILRC: Internal low-speed oscillator RC type. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 51... -
Page 52: Normal Mode
Note: If the system is in normal mode, to set STPHX=1 to disable the high clock oscillator. The system is under no system clock condition. This condition makes the system stay as power down mode, and can be wake-up by P0, P1 level change trigger. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 52... -
Page 53: Green Mode
PWM output functions active in green mode, but the timer can‟t wake-up the system as overflow. Note: Sonix provides “GreenMode” macro to control green mode operation. It is necessary to use “GreenMode” macro to control system inserting green mode. -
Page 54: Operating Mode Control Macro
SN8P2740 Series ADC, OP-amp, Comparator 8-Bit Micro-Controller 5.6 OPERATING MODE CONTROL MACRO Sonix provides operating mode control macros to switch system operating mode easily. Macro Length Description SleepMode 1-word The system insets into Sleep Mode (Power Down Mode). GreenMode 3-word The system inserts into Green Mode. -
Page 55: Wakeup
The wakeup time is as the following. The wakeup time = 1/Fosc * 32 = 2 us (Fhosc = 16MHz) Note: The high clock start-up time is depended on the VDD and oscillator type of high clock. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 55... -
Page 56: P1W Wakeup Control Register
Bit 0 P16W P15W P14W P13W P12W P11W P10W Read/Write After reset Bit[6:0] P10W~P16W: Port 1 wakeup function control bits. 0 = Disable P1n wakeup function. 1 = Enable P1n wakeup function. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 56... -
Page 57: Interrupt
INTRQ ADCIRQ 7-Bit Enable ADC Converting End Latchs CM0IRQ Comparator 0 Trigger Gating CM1IRQ Comparator 1 Trigger CM2IRQ Comparator 2 Trigger Note: The GIE bit must enable during all interrupt operation. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 57... -
Page 58: Inten Interrupt Enable Register
TC0IEN: TC0 timer interrupt control bit. 0 = Disable TC0 interrupt function. 1 = Enable TC0 interrupt function. Bit 7 ADCIEN: ADC interrupt control bit. 0 = Disable ADC interrupt function. 1 = Enable ADC interrupt function. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 58... -
Page 59: Intrq Interrupt Request Register
TC0IRQ: TC0 timer interrupt request flag. 0 = None TC0 interrupt request. 1 = TC0 interrupt request. Bit 7 ADCIRQ: ADC interrupt request flag. 0 = None ADC interrupt request. 1 = ADC interrupt request. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 59... -
Page 60: Gie Global Interrupt Operation
0 = Disable global interrupt. 1 = Enable global interrupt. Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE Note: The GIE bit must enable during all interrupt operation. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 60... -
Page 61: Push, Pop Routine
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine executed. START INT_SERVICE START: … INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector … ENDP Version 2.0 SONiX TECHNOLOGY CO., LTD Page 61... -
Page 62: External Interrupt Operation (Int0)
6.6 EXTERNAL INTERRUPT OPERATION (INT0) Sonix provides 1 external interrupt sources in the micro-controller. INT0 is external interrupt trigger sources and build in edge trigger configuration function. When the external edge trigger occurs, the external interrupt request flag will be set to “1”... -
Page 63: T0 Interrupt Operation
A, #64H B0MOV T0C, A ; Reset T0C. … ; T0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 2.0 SONiX TECHNOLOGY CO., LTD Page 63... -
Page 64: Tc0 Interrupt Operation
A, #64H B0MOV TC0C, A ; Reset TC0C. … ; TC0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 2.0 SONiX TECHNOLOGY CO., LTD Page 64... -
Page 65: Adc Interrupt Operation
; ADCIRQ = 0, exit interrupt vector B0BCLR FADCIRQ ; Reset ADCIRQ … ; ADC interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 2.0 SONiX TECHNOLOGY CO., LTD Page 65... -
Page 66: Comparator Interrupt Operation (Cmp0~Cmp2)
ADC, OP-amp, Comparator 8-Bit Micro-Controller 6.10 COMPARATOR INTERRUPT OPERATION (CMP0~CMP2) Sonix provides 3 sets comparator with interrupt function in the micro-controller. The comparator interrupt trigger edge direction is controlled by comparator register. CM0G of CM0M is control comparator 0 interrupt trigger edge direction. -
Page 67: Multi-Interrupt Operation
B0BTS0 FADCIRQ ; Check ADCIRQ INTADC ; Jump to ADC interrupt service routine … … INT_EXIT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 2.0 SONiX TECHNOLOGY CO., LTD Page 67... -
Page 68: I/O Port
P1.6 CM1P CM1EN=1, CM1RS[2:0]=000b AIN0 ADENB=1, GCHS=1, CHS[2:0] = 000b P4.0 AVREFH ADENB=1, AVREFH=1 P4[7:1] AIN[7:1] ADENB=1, GCHS=1, CHS[2:0] = 001b~111b * DC: Digital Characteristic. AC: Analog Characteristic. HV: High Voltage Characteristic. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 68... -
Page 69: I/O Port Mode
A, #0FFH ; Set all ports to be output mode. B0MOV P0M, A B0MOV P4M,A B0BCLR P4M.0 ; Set P4.0 to be input mode. B0BSET P4M.0 ; Set P4.0 to be output mode. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 69... -
Page 70: I/O Pull Up Register
Note:P0.4 is input only pin and without pull-up resister. The P0UR.4 is undefined. Example: I/O Pull up Register A, #0FFH ; Enable Port0, 4 Pull-up register, B0MOV P0UR, A B0MOV P4UR,A Version 2.0 SONiX TECHNOLOGY CO., LTD Page 70... -
Page 71: I/O Port Data Register
; Write data FFH to all Port. B0MOV P0, A B0MOV P4, A Example: Write one bit data to output port. ; Set P4.0 to be “1”. B0BSET P4.0 ; Set P4.0 to be “0”. B0BCLR P4.0 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 71... -
Page 72: Port 4 Adc Share Pin
Note: For P4.n general purpose I/O function, users should make sure of P4.n’s ADC channel is disabled, or P4.n is automatically set as ADC analog input when GCHS = 1 and CHS[2:0] point to P4.n. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 72... - Page 73 ;If CHS[2:0] don’t point to P4.0 (CHS[2:0] ≠ 000B), don’t care GCHS status. ; Clear P4CON. B0BCLR P4CON.0 ; Enable P4.0 digital function. ; Enable P4.0 input mode. B0BCLR P4M.0 ; Set P4.0 as input mode. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 73...
- Page 74 ; Set P4.0 output buffer to avoid glitch. ; Set P4.0 buffer as “1”. B0BSET P4.0 ; or ; Set P4.0 buffer as “0”. B0BCLR P4.0 ; Enable P4.0 output mode. B0BSET P4M.0 ; Set P4.0 as input mode. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 74...
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Page 75: Timers
; Clear the watchdog timer. B0MOV WDTR, A … CALL SUB1 CALL SUB2 … MAIN Example: Clear watchdog timer by “@RST_WDT” macro of Sonix IDE. Main: @RST_WDT ; Clear the watchdog timer. … CALL SUB1 CALL SUB2 … MAIN Version 2.0... - Page 76 ; I/O and RAM are correct. Clear watchdog timer and ; execute program. A, #5AH ; Clear the watchdog timer. B0MOV WDTR, A … CALL SUB1 CALL SUB2 … … … MAIN Version 2.0 SONiX TECHNOLOGY CO., LTD Page 76...
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Page 77: T0 8-Bit Basic Timer
0x00 or “n” 0xFE 0xFF by program by program or n+1 or n+2 or n+2 T0IRQ T0 timer overflows. T0IRQ set as “1”. Reload T0C by program. T0IRQ is cleared by program. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 77... -
Page 78: T0M Mode Register
T0C initial value = 256 - (T0 interval time * input clock) = 256 - (10ms * 16MHz / 16 / 128) = 256 - (10 * 16MHz / 16 / 128) = B2H Version 2.0 SONiX TECHNOLOGY CO., LTD Page 78... -
Page 79: T0 Timer Operation Explame
; Set T0C register for T0 Interval time. A, #value B0MOV T0C, A ; Clear T0IRQ B0BCLR FT0IRQ ; Enable T0 timer and interrupt function. B0BSET FT0IEN ; Enable T0 interrupt function. B0BSET FT0ENB ; Enable T0 timer. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 79... -
Page 80: Tc0 8-Bit Timer/Counter
÷16 8-Bit Binary Up Pulse Generator P0.1 Pin ÷32 Counting Counter Fhosc ÷64 TC0PO PWM0OUT=1, TC0PO=0 ÷128 ÷256 CPUM0,1 Compare TC0D Data Buffer PWM0OUT PWM0OUT=0, TC0PO=0 Comparator 0 output P0.1 Output CM0SF Version 2.0 SONiX TECHNOLOGY CO., LTD Page 80... -
Page 81: Tc0 Timer Operation
4.096 16.384 001b Fhosc/128 2.048 8.192 010b Fhosc/64 1.024 4.096 011b Fhosc/32 0.512 2.048 100b Fhosc/16 0.256 1.024 101b Fhosc/8 0.128 0.512 110b Fhosc/4 0.064 0.25 0.256 111b Fhosc/2 0.032 0.125 0.128 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 81... -
Page 82: Pulse Width Modulation (Pwm)
GPIO mode (output high). PWM Output High impendence (floating) TC0DIR=1 PWM0OUT=0. PWM0OUT=1. PWM0OUT=1. The pin exchanges to output PWM0OUT=0. The pin exchanges mode and outputs PWM signal automatically. to last GPIO mode (input). Version 2.0 SONiX TECHNOLOGY CO., LTD Page 82... -
Page 83: Tc0 Pulse Generator Function
If the trigger is comparator 0 output edge (rising edge and falling edge controlled by comparator control register‟s CM0G bit), pulse starts to output as trigger edge condition occurrence. When TC0 overflows, pulse output pin returns to idle status. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 83... - Page 84 TC0 overflows. TC0C reloads from TC0R. Comparator output signal. CM0G=0, falling edge. Comparator output signal. CM0G=1, rising edge. TC0IRQ TC0IRQ is set as TC0 overflow. TC0IRQ is cleared by program. Pulse Generator. TC0DIR=0 Pulse Generator. TC0DIR=1 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 84...
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Page 85: Tc0M Mode Register
TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0 Read/Write After reset The equation of TC0C initial value is as following. TC0C initial value = 256 - (TC0 interrupt interval time * TC0 clock rate) Version 2.0 SONiX TECHNOLOGY CO., LTD Page 85... -
Page 86: Tc0R Auto-Reload Register
100Hz. In 1/3 duty condition, the high pulse width is about 3.33ms. TC0D initial value = B2H + (PWM high pulse width period / TC0 clock rate) = B2H + (3.33ms * 16MHz / 16 / 128) = B2H + 1AH = CCH Version 2.0 SONiX TECHNOLOGY CO., LTD Page 86... -
Page 87: Tc0 Timer Operation Explame
; High pulse and low idle status. ; or B0BSET FTC0DIR ; Low pulse and high idle status. ; Enable PWM and TC0 timer. B0BSET FPWM0OUT ; Enable PWM. B0BSET FTC0ENB ; Enable TC0 timer. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 87... - Page 88 B0BSET FCM0SF ; Pulse output trigger source is comparator 0 output edge. ; Enable pulse output and TC0 timer. B0BSET FTC0PO ; Enable pulse output function. B0BSET FTC0ENB ; Enable TC0 timer. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 88...
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Page 89: Analog Comparaotr 0
Comparator Output Delay: 0, 1/Fhosc, 2/Fhosc, 3/Fhosc, 4/Fhosc, 5/Fhosc, 6/Fhosc, GPIO CM0IRQ 7/Fhosc, 8/Fhosc, 9/Fhosc, GPIO/CM0N Pin 10/Fhosc, 11/Fhosc, 12/Fhosc, CM0SF 13/Fhosc, 14/Fhosc, 15/Fhosc CM0EN TC0 Pulse Generator GPIO GPIO/CM0O Pin CM0OUT flag CM0OEN Version 2.0 SONiX TECHNOLOGY CO., LTD Page 89... -
Page 90: Normal Comparator Mode
CM0IRQ, CM0G=0 falling edge CM0IRQ sets as falling edge. CM0IRQ sets as falling edge. CM0IRQ, CM0G=1 rising edge CM0IRQ sets as rising edge. CM0IRQ sets as rising edge. *. CM0IRQ is cleared by program. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 90... - Page 91 0.5625 0.625 0.6875 0.75 0.8125 0.875 0.9375 Fhosc=16MHz Delay time (us) 2.25 2.75 3.25 3.75 Fhosc=4MHz CM0P CM0N CM0OUT without delay. CM0OUT with delay. The delay time is controlled by CM0D[3:0] bits. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 91...
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Page 92: Comparator 0 Special Fucniton
Idle High. Falling Edge Trigger. TC0 Pulse Generator Idle Low. Falling Edge Trigger. TC0 Pulse Generator Idle High. Rising Edge Trigger. TC0 Pulse Generator Idle Low. Rising Edge Trigger. TC0 pulse generator output signal with delay. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 92... -
Page 93: Comparator Mode Register
In hardware application circuit, the comparator input pins must be connected a 0.1uF comparator to reduce power noise and make the input signal more stable. The application circuit is as following. Comparator CMnO Output Comparator CMnN Negative Input 0.1uF Comparator CMnP Positive Input 0.1uF Version 2.0 SONiX TECHNOLOGY CO., LTD Page 93... -
Page 94: Comparator 0 Operation Explame
A, #11110000b A, #0000nnnnb B0MOV CMDB0, A ; Clear CM0IRQ B0BCLR FCM0IRQ ; Enable Comparator 0 and interrupt function. B0BSET FCM0IEN ; Enable Comparator 0 interrupt function. B0BSET FCM0EN ; Enable Comparator 0. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 94... -
Page 95: Analog Comparaotr 1
0, 2/Fcpu, 4/Fcpu, 6/Fcpu, 8/Fcpu, 10/Fcpu, 12/Fcpu, GPIO CM1IRQ 14/Fcpu, 16/Fcpu, 18/Fcpu, GPIO/CM1N Pin 20/Fcpu, 22/Fcpu, 24/Fcpu, CM1SF 26/Fcpu, 28/Fcpu, 30/Fcpu CM1EN Stop TC0 Pulse Generator GPIO GPIO/CM1O Pin CM1OUT flag CM1OEN Version 2.0 SONiX TECHNOLOGY CO., LTD Page 95... -
Page 96: Normal Comparator Mode
CM1G = 1, the comparator 1 interrupt trigger direction is rising edge. Note: CM1OUT is comparator raw output without latch. It varies depend on the comparator process result. But the CM1IRQ is latch comparator output result. It must be cleared by program. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 96... - Page 97 20/Fcpu 22/Fcpu 24/Fcpu 26/Fcpu 28/Fcpu 30/Fcpu Delay time (us) Fcpu=Fhosc/4 =16MHz/4=4MHz Delay time (us) Fcpu=Fhosc/16 =16MHz/16=1MHz CM1P CM1N CM1OUT without delay. CM1OUT with delay. The delay time is controlled by CM1D[3:0] bits. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 97...
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Page 98: Comparator 1 Special Fucniton
Note: If TC0 pulse output is stopped by comparator 1 special mode trigger, the CM1SF and TC0PO bits are cleared automatically. It is necessary to set CM1SF, TC0PO and TC0ENB bits by program to recover TC0 pulse generator function. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 98... -
Page 99: Comparator Mode Register
CM0D3 CM0D2 CM0D1 CM0D0 Read/Write After Reset Bit [7:4] CM1D[3:0]: Comparator 1 de-bounce time control bit. 0000=No delay, 0001=2/Fcpu, 0010=4/Fcpu, 0011=6/Fcpu, 0100=8/Fcpu, 0101=10/Fcpu, 0110=12/Fcpu,0111=14/Fcpu, 1000=16/Fcpu, 1001=18/Fcpu, 1010=20/Fcpu, 1011=22/Fcpu, 1100=24/Fcpu, 1101=26/Fcpu, 1110=28/Fcpu, 1111=30/Fcpu Version 2.0 SONiX TECHNOLOGY CO., LTD Page 99... -
Page 100: Comparator Application Notice
A, #00001111b A, #nnnn0000b B0MOV CMDB0, A ; Clear CM1IRQ B0BCLR FCM1IRQ ; Enable Comparator 1 and interrupt function. B0BSET FCM1IEN ; Enable Comparator 1 interrupt function. B0BSET FCM1EN ; Enable Comparator 1. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 100... -
Page 101: Analog Comparaotr 2
0, 2/Fcpu, 4/Fcpu, 6/Fcpu, 8/Fcpu, 10/Fcpu, 12/Fcpu, GPIO CM2IRQ 14/Fcpu, 16/Fcpu, 18/Fcpu, GPIO/CM2N Pin 20/Fcpu, 22/Fcpu, 24/Fcpu, CM2SF 26/Fcpu, 28/Fcpu, 30/Fcpu Increase TC0R to CM2EN shrink TC0 Pulse width GPIO GPIO/CM2O Pin CM2OUT flag CM2OEN Version 2.0 SONiX TECHNOLOGY CO., LTD Page 101... -
Page 102: Normal Comparator Mode
CM2G = 1, the comparator 2 interrupt trigger direction is rising edge. Note: CM2OUT is comparator raw output without latch. It varies depend on the comparator process result. But the CM2IRQ is latch comparator output result. It must be cleared by program. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 102... - Page 103 20/Fcpu 22/Fcpu 24/Fcpu 26/Fcpu 28/Fcpu 30/Fcpu Delay time (us) Fcpu=Fhosc/4 =16MHz/4=4MHz Delay time (us) Fcpu=Fhosc/16 =16MHz/16=1MHz CM2P CM2N CM2OUT without delay. CM2OUT with delay. The delay time is controlled by CM2D[3:0] bits. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 103...
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Page 104: Comparator 2 Special Fucniton
Pulse width keeps last period. TC0R+1 pulse width. TC0R+2 pulse width. Note: If TC0R is increased to 0xFF, TC0R will keep 0xFF and not increase again, even the comparator output status never occurs exchanging. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 104... -
Page 105: Comparator Mode Register
CM2D3 CM2D2 CM2D1 CM2D0 Read/Write After Reset Bit [7:4] CM2D[3:0]: Comparator 2 de-bounce time control bit. 0000=No delay, 0001=2/Fcpu, 0010=4/Fcpu, 0011=6/Fcpu, 0100=8/Fcpu, 0101=10/Fcpu, 0110=12/Fcpu,0111=14/Fcpu, 1000=16/Fcpu, 1001=18/Fcpu, 1010=20/Fcpu, 1011=22/Fcpu, 1100=24/Fcpu, 1101=26/Fcpu, 1110=28/Fcpu, 1111=30/Fcpu Version 2.0 SONiX TECHNOLOGY CO., LTD Page 105... -
Page 106: Comparator Application Notice
; Set CM2D[3:0] for comparator output de-bounce. B0MOV CMDB1, A ; Clear CM2IRQ B0BCLR FCM2IRQ ; Enable Comparator 2 and interrupt function. B0BSET FCM2IEN ; Enable Comparator 2 interrupt function. B0BSET FCM2EN ; Enable Comparator 2. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 106... -
Page 107: 4K Buzzer Generator
1. If BZEN=0, the buzzer output pin is GPIO mode and returns to last status after disabling buzzer output. 2. If BZEN=1, the buzzer output pin is buzzer output function and isolates the GPIO function. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 107... -
Page 108: Channel Analog To Digital Converter (Adc)
AIN2/ ADC High ADC Clock Reference Voltage Counter P4.2 AIN3/ GCHS 8/12 P4.3 SAR ADC ADB[11:0] Analog Input AIN4/ P4.4 ADC Offset ADCIRQ Calibration AIN5/ P4.5 AIN6/ ADENB ADS P4.6 AIN7/ P4.7 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 108... -
Page 109: Adc Mode Register
ADCKS [1:0]: ADC‟s clock rate select bit. Bit 6,4 00 = Fcpu/16, 01 = Fcpu/8, 10 = Fcpu/1, 11 = Fcpu/2 ADLEN: ADC‟s resolution select bits. Bit 5 0 = 8-bit. 1 = 12-bit. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 109... -
Page 110: Adc Data Buffer Registers
8-bit 9-bit 10-bit 11-bit 12-bit O = Selected, x = Useless Note: The initial status of ADC data buffer including ADB register and ADR low-nibble after the system reset is unknown. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 110... -
Page 111: Adc Operation Description And Notic
41.667KHz Fcpu/8 = 96 us = 24 us 0 (8-bit) 1/(4MHz/4)*12 83.333KHz 1/(16MHz/4)*12 333.333KHz Fcpu = 12 us = 3 us 1/(4MHz/2/4)*12 41.667KHz 1/(16MHz/2/4)*12 166.667KHz Fcpu/2 = 24 us = 6 us Version 2.0 SONiX TECHNOLOGY CO., LTD Page 111... -
Page 112: Adc Pin Configuration
1 = P4.n is pure analog input, can‟t be a digital I/O pin. Note: When Port 4.n is general I/O port not ADC channel, P4CON.n must set to “0” or the Port 4.n digital I/O signal would be isolated. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 112... -
Page 113: Adc Operation Examlpe
ADENB is set one time when the system under normal run condition, and do the delay time only one time. In power saving situation like power down mode and green mode, and not using ADC function, to disable ADC by program is necessary to reduce power consumption. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 113... - Page 114 Note: ADS is cleared when the end of ADC converting automatically. EOC bit indicates ADC processing status immediately and is cleared when ADS = 1. Users needn’t to clear ADS bit by program. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 114...
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Page 115: Adc Application Circuit
These capacitors are set between AVREFH pin and VSS pin, and must be on the side of the AVREFH pin as possible. Don‟t connect the capacitor‟s ground pin to ground plain directly, and must be through VSS pin. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 115... -
Page 116: Rail To Rail Op Amplifer
Bit 0 OPEN Read/Write After Reset Bit 0 OPEN: OP Amp control bit. 0 = Disable. P1.0, P1.1, P1.2 are GPIO mode. 1 = Enable. P1.0, P1.1, P1.2 are OP Amp pins. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 116... -
Page 117: Instruction Table
Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1. 2. If branch condition is true then “S = 1”, otherwise “S = 0”. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 117... -
Page 118: Electrical Characteristic
Low voltage reset/indicator level. -40 C~85 Low voltage reset/indicator level. 25 Vdet2 Low voltage reset/indicator level. -40 C~85 “ ” These parameters are for design reference, not tested. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 118... - Page 119 Output Slew Rate Tosr Vdd=3V Comparator output voltage transitions from Vdd to Vss. Vdd=5V Common Mode Input Voltage Vcmr Vdd=5.0V Vss+0.5 Vdd-0.5 Range “ ” These parameters are for design reference, not tested. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 119...
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Page 120: Characteristic Graphs
The Graphs in this section are for design guidance, not tested or guaranteed. In some graphs, the data presented are outside specified operating range. This is for information only and devices are guaranteed to operate properly only within the specified range (-40℃~+85℃ curves are for design reference). Version 2.0 SONiX TECHNOLOGY CO., LTD Page 120... -
Page 121: Development Tool
Writer transition board: SN8P2742 / SN8P2743 17.1 SN8P2740 EV-KIT SONIX provides SN8P2740 series MCU which includes PWM, ADC, Comparator and OP analog functions. These functions aren‟t built in SN8ICE2K Plus 2. To emulate the functions must be through SN8P2743 real chip. The real chip provides an EV-KIT to achieve PWM and the analog functions emulations. - Page 122 C19: CMP2 positive input pin‟s 0.1F bypass capacitor. C20: CMP2 negative input pin‟s 0.1F bypass capacitor. JP24: Chip select (SN8P2742: Jumper short, SN8P2743: Open). JP25: P0.1 output MOS circuit power source Version 2.0 SONiX TECHNOLOGY CO., LTD Page 122...
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Page 123: Ice And Ev-Kit Application Notic
5. User observes EV-KIT‟s power LED (D1) is light after turn on SN8ICE2K Plus power switch. If LED (D1) is not light, that means, user contact to SONIX‟s agent right now. 6. If user program select chip SN8P2743, JP24 open. Or user program select chip SN8P2742, JP24 short (Jumper). - Page 124 22. When user uses CMP0‟s de-bounce time control (CM0D3~CM0D0 and clock source is Fhosc) in ICE emulation. If user sets IDE breakpoint, the CM0O output will be not effected (Fhosc still work). Version 2.0 SONiX TECHNOLOGY CO., LTD Page 124...
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Page 125: Otp Programming Pin
JP1 for Writer transition board DIP13 DIP36 JP2 for dice and >48 pin package DIP14 DIP35 DIP15 DIP34 DIP16 DIP33 DIP17 DIP32 DIP18 DIP31 DIP19 DIP30 DIP20 DIP29 DIP21 DIP28 DIP22 DIP27 DIP23 DIP26 DIP24 DIP25 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 125... -
Page 126: Programming Pin Mapping
Writer Connector IC and JP3 48-pin text tool Pin Assignment JP1/JP2 JP1/JP2 Pin Number Pin Name Pin Number Pin Name Pin Number Pin Number Pin Name Pin Number P4.0 P4.4 P4.1 ALSB/PDB XOUT/P0.5 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 126... -
Page 127: Marking Definition
Marking Definition 19.1 INTRODUCTION There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit MCU for order or obtain information. This definition is only for Blank OTP MCU. 19.2 MARKING INDETIFICATION SYSTEM SN8 X PART No. -
Page 128: Marking Example
PB-Free Package -40℃~85℃ SN8P2742PDB 2743 PB-Free Package SN8P2742SDB -40℃~85℃ 2743 PB-Free Package -20℃~70℃ SN8P27411PB 2743 PB-Free Package -20℃~70℃ SN8P27411SB 2743 PB-Free Package -40℃~85℃ SN8P27411PDB 2743 PB-Free Package -40℃~85℃ SN8P27411SDB 2743 PB-Free Package Version 2.0 SONiX TECHNOLOGY CO., LTD Page 128... -
Page 129: Datecode System
..9=09 A=10 B=11 ..1=January Month 2=February ..9=September A=October B=November C=December 03= 2003 Year 04= 2004 05= 2005 06= 2006 ..Version 2.0 SONiX TECHNOLOGY CO., LTD Page 129... -
Page 130: Package Information
31.750 32.512 0.300 BSC 7.620 BSC 0.253 0.258 0.263 6.426 6.553 6.680 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.335 0.355 0.375 8.509 9.017 9.525 θ° 0° 7° 15° 0° 7° 15° Version 2.0 SONiX TECHNOLOGY CO., LTD Page 130... -
Page 131: Sop 24 Pin
0.254 0.612 0.618 0.624 15.545 15.697 15.850 0.292 0.296 0.299 7.417 7.518 7.595 0.405 0.412 0.419 10.287 10.465 10.643 0.021 0.031 0.041 0.533 0.787 1.041 θ° 0° 4° 8° 0° 4° 8° Version 2.0 SONiX TECHNOLOGY CO., LTD Page 131... -
Page 132: P-Dip 20 Pin
1.060 24.892 26.162 26.924 0.300 7.620 0.245 0.250 0.255 6.223 6.350 6.477 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.335 0.355 0.375 8.509 9.017 9.525 θ° 0° 7° 15° 0° 7° 15° Version 2.0 SONiX TECHNOLOGY CO., LTD Page 132... -
Page 133: Sop 20 Pin
0.305 0.496 0.502 0.508 12.598 12.751 12.903 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.325 10.643 0.016 0.033 0.050 0.406 0.838 1.270 θ° 0° 4° 8° 0° 4° 8° Version 2.0 SONiX TECHNOLOGY CO., LTD Page 133... -
Page 134: P-Dip 16 Pin
0.775 18.669 19.177 19.685 0.300BSC 7.620BSC 0.245 0.250 0.255 6.223 6.350 6.477 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.335 0.355 0.375 8.509 9.017 9.525 θ° 0° 7° 15° 0° 7° 15° Version 2.0 SONiX TECHNOLOGY CO., LTD Page 134... -
Page 135: Sop 16 Pin
0.25 0.049 1.25 0.012 0.020 0.31 0.51 0.004 0.010 0.10 0.25 9.90BSC 9.90BSC 6.00BSC 6.00BSC 3.90BSC 3.90BSC 1.27BSC 1.27BSC 0.016 0.050 0.40 1.27 0.010 0.020 0.25 0.50 θ° 0° 8° 0° 8° Version 2.0 SONiX TECHNOLOGY CO., LTD Page 135... - Page 136 SONIX product could create a situation where personal injury or death may occur.
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