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SN8P275X Series
USER'S MANUAL
Version 0.7
SN8P2754
SN8P2755
SN8P2758
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
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Page 1
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
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Version 0.7
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Summary of Contents for SONIX SN8P2754
- Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.
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Page 2: Amendent History
1. Update code option table. VER 0.7 Nov. 2009 1. Modify LQFP48 marking name 2. Add AVDD pin descriptment 3. Modify DAO as 7bit DAC output in 1.4 Pin Description 4. Fix typing error Version 0.7 SONiX TECHNOLOGY CO., LTD Page 2... -
Page 3: Table Of Contents
ADDRESSING MODE ........................39 2.2.1 IMMEDIATE ADDRESSING MODE ..................39 2.2.2 DIRECTLY ADDRESSING MODE ..................39 2.2.3 INDIRECTLY ADDRESSING MODE ................... 39 STACK OPERATION........................40 2.3.1 OVERVIEW..........................40 2.3.2 STACK REGISTERS....................... 41 Version 0.7 SONiX TECHNOLOGY CO., LTD Page 3... - Page 4 SYSTEM OPERATION MODE ......................59 OVERVIEW............................. 59 SYSTEM MODE SWITCHING....................... 60 WAKEUP ............................62 5.3.1 OVERVIEW..........................62 5.3.2 WAKEUP TIME ........................62 5.3.3 P1W WAKEUP CONTROL REGISTER ................63 INTERRUPT............................64 OVERVIEW............................. 64 Version 0.7 SONiX TECHNOLOGY CO., LTD Page 4...
- Page 5 TC0 TIMER NOTICE ......................96 TIMER/COUNTER 1 (TC1) ......................97 8.4.1 OVERVIEW..........................97 8.4.2 TC1M MODE REGISTER....................... 98 8.4.3 TC1C COUNTING REGISTER ....................99 8.4.4 TC1R AUTO-LOAD REGISTER..................100 8.4.5 TC1 CLOCK FREQUENCY OUTPUT (BUZZER).............. 101 Version 0.7 SONiX TECHNOLOGY CO., LTD Page 5...
- Page 6 Mater Mode Support....................... 128 10.8.2 MSP Rate Generator....................... 128 10.8.3 MSP Mater START Condition ....................129 10.8.4 MSP Master mode Repeat START Condition ............... 130 10.8.5 Acknowledge Sequence Timing..................... 131 10.8.6 STOP Condition Timing......................132 Version 0.7 SONiX TECHNOLOGY CO., LTD Page 6...
- Page 7 SN8P275X Series Programming Pin Mapping: ..............149 PACKAGE INFORMATION ......................150 16.1 SK-DIP28 PIN ..........................150 16.2 SOP28 PIN............................151 16.3 P-DIP 32 PIN ..........................152 16.4 SOP 32 PIN............................. 152 16.5 SSOP 48 PIN........................... 153 Version 0.7 SONiX TECHNOLOGY CO., LTD Page 7...
- Page 8 8-bit micro-controller build-in 12-bit ADC 16.6 LQFP 48 PIN ..........................154 MARKING DEFINITION........................155 17.1 INTRODUCTION .......................... 155 17.2 MARKING INDETIFICATION SYSTEM..................155 17.3 MARKING EXAMPLE ......................... 156 17.4 DATECODE SYSTEM ........................156 Version 0.7 SONiX TECHNOLOGY CO., LTD Page 8...
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Page 9: Product Overview
♦ Memory configuration SN8P2755: PDIP 32 pins, SOP 32 pins OTP ROM size: 4K * 16 bits. SN8P2754: SK-DIP 28 pins, SOP 28pins RAM size: 256 * 8 bits (bank 0 and bank 1). Eight levels stack buffer ♦ ♦ Three 8-bit Timer/Counter... -
Page 10: System Block Diagram
I/O ADC DAC Pin no. T0 TC0 TC1 Buzzer SN8P2758 4K*16 256 36 8ch 1ch SSOP48/LQFP48 SN8P2755 4K*16 256 23 8ch 1ch DIP32/SOP32 SN8P2754 4K*16 256 18 5ch 1ch SKDIP28/SOP28 1.2 SYSTEM BLOCK DIAGRAM system block system block Internal Internal H-OSC H-OSC... -
Page 11: Pin Assignment
24 P4.0/AIN0 P1.4 10 23 P4.1/AIN1 P1.3 11 22 P4.2/AIN2 P1.2 12 21 P4.3/AIN3 SDA/P1.1 13 20 P4.4/AIN4 SCL/P1.0 14 19 P4.5/AIN5 P2.0 15 18 P4.6/AIN6 VSS 16 17 P4.7/AIN7 SN8P2755P SN8P2755S Version 0.7 SONiX TECHNOLOGY CO., LTD Page 11... - Page 12 VDD 8 29 P4.5/AIN5 P0.0/INT0 9 28 P4.6/AIN6 P0.1/INT1 10 27 P4.7/AIN7 P0.2/INT2 11 26 AVREFL RST/VPP/P3.3 12 25 VSS 13 14 15 16 17 18 19 20 21 22 23 24 Version 0.7 SONiX TECHNOLOGY CO., LTD Page 12...
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Page 13: Pin Descriptions
TC0 ÷ 2 signal output pin for buzzer or PWM0 output pin. AVDD Power supply input pins for A/D circuit AVREFH ADC highest reference voltage input AVREFL ADC lowest reference voltage input 7bit DAC output Version 0.7 SONiX TECHNOLOGY CO., LTD Page 13... -
Page 14: Pin Circuit Diagrams
Port 0, 1, 2, 3, 5 structure: Pull-Up PnM, PnUR Input Bus Output Output Bus Latch Port 4 structure: Pull-Up P4CON PnM, PnUR Input Bus Output Output Bus Latch GCHS Int. ADC Version 0.7 SONiX TECHNOLOGY CO., LTD Page 14... -
Page 15: Central Processor Unit (Cpu)
Jump to user start address 0001H General purpose area 0007H 0008H Interrupt vector User interrupt vector 0009H User program 000FH 0010H 0011H General purpose area FFBH End of user program FFCH FFDH Reserved FFEH FFFH Version 0.7 SONiX TECHNOLOGY CO., LTD Page 15... -
Page 16: Reset Vector (0000H)
; Jump to user program address. … ; Interrupt vector. PUSH ; Save ACC and PFLAG register to buffers. … … ; Load ACC and PFLAG register from buffers. RETI ; End of interrupt service routine … Version 0.7 SONiX TECHNOLOGY CO., LTD Page 16... - Page 17 SN8P275X Series 8-bit micro-controller build-in 12-bit ADC START: ; The head of user program. … ; User program … START ; End of user program … ENDP ; End of program Version 0.7 SONiX TECHNOLOGY CO., LTD Page 17...
- Page 18 ENDP ; End of program. Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
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Page 19: Look-Up Table Description
INC_XYZ macro shows a simple method to process X, Y and Z registers automatically. Example: INC_XYZ macro. INC_XYZ MACRO INCMS ; Z+1 ; Not overflow INCMS ; Y+1 ; Not overflow INCMS ; X+1 ; Not overflow ENDM Version 0.7 SONiX TECHNOLOGY CO., LTD Page 19... - Page 20 ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 … TABLE1: 0035H ; To define a word (16 bits) data. 5105H 2012H … Version 0.7 SONiX TECHNOLOGY CO., LTD Page 20...
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Page 21: Jump Table Description
; ACC = 3, jump to A3POINT SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size. - Page 22 SN8P275X Series 8-bit micro-controller build-in 12-bit ADC Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”. B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A ; The number of the jump table listing is five. A0POINT ; ACC = 0, jump to A0POINT A1POINT ;...
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Page 23: Checksum Calculation
; If Not jump to checksum calculate CHECKSUM_END ; If Yes checksum calculated is done. Y_ADD_1: INCMS ; Increase Y ; Jump to checksum calculate CHECKSUM_END: … … END_USER_CODE: ; Label of program end Version 0.7 SONiX TECHNOLOGY CO., LTD Page 23... -
Page 24: Code Option Table
Fcpu code option is only available for High Clock. Fcpu of slow mode is Flosc/4. In external RC mode, the Noise_Filter is enabled by assembler. If watchdog enable, watchdog timer is still counting in green mode. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 24... -
Page 25: Data Memory (Ram)
End of bank 0 area 100h 100h~17Fh of Bank 1 = To store general purpose data (128 bytes). “ “ General purpose area BANK 1 “ “ “ 17Fh End of bank 1 area Version 0.7 SONiX TECHNOLOGY CO., LTD Page 25... -
Page 26: System Register
STKP = Stack pointer buffer. STK0~STK7 = Stack 0 ~ stack 7 buffer. @HL = RAM HL indirect addressing index pointer. @YZ = RAM YZ indirect addressing index pointer. P4CON= Port 4 configuration setting Version 0.7 SONiX TECHNOLOGY CO., LTD Page 26... -
Page 27: Bit Definition Of System Register
MSPADR 095H 096H 097H 098H 099H 09AH 09BH 09CH 09DH 09EH 09FH Address 0A0H ~ 0BFH Addr Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Name 0A0H 0A1H 0A2H 0A3H 0A4H Version 0.7 SONiX TECHNOLOGY CO., LTD Page 27... - Page 28 SIOIRQ P02IRQ P01IRQ P00IRQ INTRQ 0C9H ADCIEN TC1IEN TC0IEN T0IEN SIOIEN P02IEN P01IEN P00IEN INTEN 0CAH CPUM1 CPUM0 CLKMD STPHX OSCM 0CBH 0CCH WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0 WDTR Version 0.7 SONiX TECHNOLOGY CO., LTD Page 28...
- Page 29 0F1H S7PC11 S7PC10 S7PC9 S7PC8 STK7H 0F2H S6PC7 S6PC6 S6PC5 S6PC4 S6PC3 S6PC2 S6PC1 S6PC0 STK6L 0F3H S6PC11 S6PC10 S6PC9 S6PC8 STK6H 0F4H S5PC7 S5PC6 S5PC5 S5PC4 S5PC3 S5PC2 S5PC1 S5PC0 STK5L Version 0.7 SONiX TECHNOLOGY CO., LTD Page 29...
- Page 30 2. All of register names had been declared in SN8ASM assembler. 3. One-bit name had been declared in SN8ASM assembler with “F” prefix code. 4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 30...
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Page 31: Accumulator
; Load ACC form buffer. RETI ; Exit interrupt service vector Note: To save and re-load ACC data, users must use “B0XCH” instruction, or else the PFLAG Register might be modified by ACC operation. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 31... -
Page 32: Program Flag
1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero. Note: Refer to instruction set table for detailed information of C, DC and Z flags. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 32... -
Page 33: Program Counter
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. A, #12H ; To skip, if ACC = 12H. CMPRS C0STEP ; Else jump to C0STEP. … … C0STEP: Version 0.7 SONiX TECHNOLOGY CO., LTD Page 33... - Page 34 DECS BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: DECMS instruction: DECMS BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: Version 0.7 SONiX TECHNOLOGY CO., LTD Page 34...
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Page 35: H, L Registers
Bit 0 LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0 Read/Write After reset Example: If want to read a data from RAM address 20H of bank_0, it can use indirectly addressing mode to Version 0.7 SONiX TECHNOLOGY CO., LTD Page 35... - Page 36 ; Clear @HL to be zero DECMS ; L – 1, if L = 0, finish the routine CLR_HL_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … … Version 0.7 SONiX TECHNOLOGY CO., LTD Page 36...
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Page 37: Y, Z Registers
Bit 3 Bit 2 Bit 1 Bit 0 XBIT7 XBIT6 XBIT5 XBIT4 XBIT3 XBIT2 XBIT1 XBIT0 Read/Write After reset Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about X register look-up table application. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 37... -
Page 38: R Registers
Bit 3 Bit 2 Bit 1 Bit 0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Read/Write After reset Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 38... -
Page 39: Addressing Mode
; To clear Y register to access RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 39... -
Page 40: Stack Operation
STKP = 5 STK5H STK5L STKP STKP STKP = 4 STK4H STK4L STKP = 3 STK3H STK3L STKP = 2 STK2H STK2L STKP = 1 STK1H STK1L STKP = 0 STK0H STK0L Version 0.7 SONiX TECHNOLOGY CO., LTD Page 40... -
Page 41: Stack Registers
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKnL SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0 Read/Write After reset STKn = STKnH , STKnL (n = 7 ~ 0) Version 0.7 SONiX TECHNOLOGY CO., LTD Page 41... -
Page 42: Stack Operation Example
STKP Register Stack Buffer Stack Level Description STKPB2 STKPB1 STKPB0 High Byte Low Byte STK7H STK7L STK6H STK6L STK5H STK5L STK4H STK4L STK3H STK3L STK2H STK2L STK1H STK1L STK0H STK0L Free Free Version 0.7 SONiX TECHNOLOGY CO., LTD Page 42... -
Page 43: Reset
High Detect Watchdog Low Detect Overflow Watchdog Normal Run Watchdog Reset Watchdog Stop System Normal Run System Status System Stop Power On External Watchdog Delay Time Reset Delay Reset Delay Time Time Version 0.7 SONiX TECHNOLOGY CO., LTD Page 43... -
Page 44: Power On Reset
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the watchdog timer function. Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 44... -
Page 45: Brown Out Reset
DC low battery condition. When turn off the AC power, the VDD drops slowly and through the dead-band for a while. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 45... -
Page 46: The System Operating Voltage Decsription
2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips) and use external reset (“ Zener diode reset circuit”, “Voltage bias reset circuit”, “External reset IC”). The structure can improve noise effective and get good EFT characteristic. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 46... - Page 47 Delay Time The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by each MCU.
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Page 48: External Reset
The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference. Note: The reset circuit is no any protection against unusual power or brown out reset. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 48... -
Page 49: Diode & Rc Reset Circuit
PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener specification. Select the right zener voltage to conform the application. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 49... -
Page 50: Voltage Bias Reset Circuit
When power drops below the reset detect voltage, the system reset would be triggered, and then system executes reset sequence. That makes sure the system work well under unstable power situation. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 50... -
Page 51: External Reset Ic
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can improve all power variation. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 51... -
Page 52: System Clock
Fcpu = Flosc/4. SONIX provides a “Noise Filter” controlled by code option. In high noisy situation, the noise filter can isolate noise outside and protect system works well. The minimum Fcpu of high clock is limited at Fhosc/4 when noise filter enable. -
Page 53: Oscm Register
Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal low-speed oscillator will be stopped. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Version 0.7 SONiX TECHNOLOGY CO., LTD Page 53... -
Page 54: System High Clock
High_Clk code option. The start up time of crystal/ceramic and RC type oscillator is different. RC type oscillator’s start-up time is very short, but the crystal’s is longer. The oscillator start-up time decides reset time length. 4MHz Crystal 32768Hz Crystal 4MHz Ceramic Version 0.7 SONiX TECHNOLOGY CO., LTD Page 54... -
Page 55: Crystal/Ceramic
“R” value is to change frequency. 50P~100P is good value for “C”. XOUT pin is general purpose I/O pin. Note: Connect the R and C as near as possible to the VDD pin of micro-controller. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 55... -
Page 56: External Clock Signal
XIN pin. XOUT pin is general purpose I/O pin. External Clock Input XOUT Note: The GND of external oscillator circuit must be as near as possible to VSS pin of micro-controller. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 56... -
Page 57: System Low Clock
; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1 (32K, watchdog disable) bits of OSCM register. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 57... -
Page 58: System Clock Measurement
; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P0.0 ; Measure the Fcpu frequency by oscilloscope. Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC frequency. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 58... -
Page 59: System Operation Mode
All active All active All active All inactive P0, P1, T0 Wakeup source P0, P1, Reset Reset EHOSC: External high clock ILRC: Internal low clock (16K RC oscillator at 3V, 32K at 5V) Version 0.7 SONiX TECHNOLOGY CO., LTD Page 59... -
Page 60: System Mode Switching
; Set CPUM1 = 1. Note: If T0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can wakeup the system backs to the previous operation mode. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 60... - Page 61 Note: During the green mode with T0 wake-up function, the wakeup pins, reset pin and T0 can wakeup the system back to the last mode. T0 wake-up period is controlled by program and T0ENB must be set. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 61...
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Page 62: Wakeup
The wakeup time is as the following. The wakeup time = 1/Fosc * 4096 = 1.024 ms (Fosc = 4MHz) The total wakeup time = 1.024ms + oscillator start-up time Version 0.7 SONiX TECHNOLOGY CO., LTD Page 62... -
Page 63: P1W Wakeup Control Register
Bit 0 P17W P16W P15W P14W P13W P12W P11W P10W Read/Write After reset Bit[7:0] P10W~P17W: Port 1 wakeup function control bits. 0 = Disable P1n wakeup function. 1 = Enable P1n wakeup function. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 63... -
Page 64: Interrupt
GIE bit will set to “1” to accept the next interrupts’ request. All of the interrupt request signals are stored in INTRQ register. Note: The GIE bit must enable during all interrupt operation. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 64... -
Page 65: Inten Interrupt Enable Register
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTEN_1 MSPIEN Read/Write After Reset Bit 0 MSPIEN: MSP interrupt control bit.. 0 = Disable 1 = Enable Version 0.7 SONiX TECHNOLOGY CO., LTD Page 65... -
Page 66: Intrq Interrupt Request Register
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTRQ_1 MSPIRQ Read/Write After Reset Bit 0 MSPIRQ: MSP interrupt request bit. 0 = No Request. 1 = Request. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 66... -
Page 67: Gie Global Interrupt Operation
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine executed. START INT_SERVICE START: … INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 67... - Page 68 SN8P275X Series 8-bit micro-controller build-in 12-bit ADC RETI ; Exit interrupt service vector … ENDP Version 0.7 SONiX TECHNOLOGY CO., LTD Page 68...
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Page 69: External Interrupt Operation (Int0~Int2)
8-bit micro-controller build-in 12-bit ADC 6.6 EXTERNAL INTERRUPT OPERATION (INT0~INT2) Sonix provides 3 sets external interrupt sources in the micro-controller. INT0, INT1 and INT2 are external interrupt trigger sources and build in edge trigger configuration function. When the external edge trigger occurs, the external interrupt request flag will be set to “1”... -
Page 70: T0 Interrupt Operation
A, #74H B0MOV T0C, A ; Reset T0C. … ; T0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.7 SONiX TECHNOLOGY CO., LTD Page 70... -
Page 71: Tc0 Interrupt Operation
A, #74H B0MOV TC0C, A ; Reset TC0C. … ; TC0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.7 SONiX TECHNOLOGY CO., LTD Page 71... -
Page 72: Tc1 Interrupt Operation
A, #74H B0MOV TC1C, A ; Reset TC1C. … ; TC1 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.7 SONiX TECHNOLOGY CO., LTD Page 72... -
Page 73: Sio Interrupt Operation
; SIOIRQ = 0, exit interrupt vector B0BCLR FSIOIRQ ; Reset SIOIRQ … ; SIO interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.7 SONiX TECHNOLOGY CO., LTD Page 73... -
Page 74: Adc Interrupt Operation
; ADCIRQ = 0, exit interrupt vector B0BCLR FADCIRQ ; Reset ADCIRQ … ; ADC interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.7 SONiX TECHNOLOGY CO., LTD Page 74... -
Page 75: Multi-Interrupt Operation
For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests. Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and interrupt request flag in interrupt routine. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 75... - Page 76 ; Jump to exit of IRQ B0BTS0 FADCIRQ ; Check ADCIRQ INTADC ; Jump to ADC interrupt service routine INT_EXIT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.7 SONiX TECHNOLOGY CO., LTD Page 76...
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Page 77: I/O Port
1 = Pn is output mode. Note: Users can program them by bit control instructions (B0BSET, B0BCLR). Note: If not used ADC function, AVDD must be connect with VDD, otherwise P4 I/O maybe ERROR. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 77... - Page 78 ; Set all ports to be output mode. B0MOV P0M, A B0MOV P4M,A B0MOV P5M, A B0BCLR P4M.0 ; Set P4.0 to be input mode. B0BSET P4M.0 ; Set P4.0 to be output mode. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 78...
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Page 79: I/O Pull Up Register
P56R P55R P54R P53R P52R P51R P50R Read/Write After reset Example: I/O Pull up Register A, #0FFH ; Enable Port0, 4, 5 Pull-up register, B0MOV P0UR, A B0MOV P4UR,A B0MOV P5UR, A Version 0.7 SONiX TECHNOLOGY CO., LTD Page 79... -
Page 80: I/O Port Data Register
Example: Write one bit data to output port. B0BSET P4.0 ; Set P4.0 and P5.3 to be “1”. B0BSET P5.3 B0BCLR P4.0 ; Set P4.0 and P5.3 to be “0”. B0BCLR P5.3 Version 0.7 SONiX TECHNOLOGY CO., LTD Page 80... -
Page 81: I/O Open-Drain Register
Note: P1OC is write only register. Setting P10OC must be used “MOV” instructions. Example: Disable P1.0 to open-drain mode and output low. A, #0 ; Disable P1.0 open-drain function. B0MOV P1OC, A Note: After disable open-drain function, I/O mode returns to last I/O mode. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 81... -
Page 82: Port 4 Adc Share Pin
CHS[2:0]: ADC input channels select bit. 000 = AIN0, 001 = AIN1, … 110 = AIN6, 111 = AIN7. Note: For P4.n general purpose I/O function, users should make sure of P4.n’s ADC channel is disabled. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 82... - Page 83 ; Set P4.1 output buffer to avoid glitch. B0BSET P4.1 ; Set P4.1 buffer as “1”. ; or B0BCLR P4.1 ; Set P4.1 buffer as “0”. ; Enable P4.1 output mode. B0BSET P4M.1 ; Set P4.1 as input mode. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 83...
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Page 84: Timers
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the main routine of the program. Main: A, #5AH ; Clear the watchdog timer. B0MOV WDTR, A … … CALL SUB1 CALL SUB2 … … MAIN Version 0.7 SONiX TECHNOLOGY CO., LTD Page 84... - Page 85 ; I/O and RAM are correct. Clear watchdog timer and ; execute program. B0BSET FWDRST ; Only one clearing watchdog timer of whole program. … CALL SUB1 CALL SUB2 … … … MAIN Version 0.7 SONiX TECHNOLOGY CO., LTD Page 85...
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Page 86: Timer 0 (T0)
Load T0TB Fcpu T0C 8-Bit Binary Up Counting Counter CPUM0,1 T0 Time Out T0ENB Note: In RTC mode, the T0 interval time is fixed at 0.5 sec and isn’t controlled by T0C. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 86... -
Page 87: T0M Mode Register
T0ENB: T0 counter control bit. 0 = Disable T0 timer. 1 = Enable T0 timer. Note: T0RATE is not available in RTC mode. The T0 interval time is fixed at 0.5 sec. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 87... -
Page 88: T0C Counting Register
4 us 31.25 ms 122.07 us Fcpu/2 0.512 ms 2 us 15.625 ms 61.035 us Note: T0C is not available in RTC mode. The T0 interval time is fixed at 0.5 sec. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 88... -
Page 89: T0 Timer Operation Sequence
Set T0 interrupt interval time. A,#7FH B0MOV T0C,A ; Set T0C value. Set T0 timer function mode. B0BSET FT0IEN ; Enable T0 interrupt function. Enable T0 timer. B0BSET FT0ENB ; Enable T0 timer. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 89... -
Page 90: Timer/Counter 0 (Tc0)
Auto. Reload TC0 / 2 P5.4 TC0R Reload Data Buffer PWM0OUT TC0 Rate Compare (Fcpu/2~Fcpu/256) TC0CKS TC0ENB Load Fcpu TC0C 8-Bit Binary Up TC0 Time Out Counting Counter INT0 (Schmitter Trigger) CPUM0,1 Version 0.7 SONiX TECHNOLOGY CO., LTD Page 90... -
Page 91: Tc0M Mode Register
0 = Disable TC0 timer. 1 = Enable TC0 timer. Note: When TC0CKS=1, TC0 became an external event counter and TC0RATE is useless. No more P0.0 interrupt request will be raised. (P0.0IRQ will be always 0). Version 0.7 SONiX TECHNOLOGY CO., LTD Page 91... -
Page 92: Tc0C Counting Register
62.5 ms 244.141 us Note: TC0C can’t be set as 0xFF when TC0 timer operating in interrupt, buzzer output modes. TC0C available range is 0x00~0xFE. The problem doesn’t exist in pure PWM mode. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 92... -
Page 93: Tc0R Auto-Load Register
= 100 = 64H Note: TC0R can’t be set as 0xFF when TC0 timer operating in interrupt, buzzer output modes. TC0R available range is 0x00~0xFE. The problem doesn’t exist in pure PWM mode. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 93... -
Page 94: Tc0 Clock Frequency Output (Buzzer)
; Enable TC0 output to P5.4 and disable P5.4 I/O function B0BSET FALOAD0 ; Enable TC0 auto-reload function B0BSET FTC0ENB ; Enable TC0 timer Note: Buzzer output is enabled, and “PWM0OUT” must be “0”. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 94... -
Page 95: Tc0 Timer Operation Sequence
; ALOAD0, TC0OUT = 01, PWM cycle boundary is 0~63. B0BSET FTC0OUT B0BSET FALOAD0 ; ALOAD0, TC0OUT = 10, PWM cycle boundary is 0~31. B0BCLR FTC0OUT B0BSET FALOAD0 ; ALOAD0, TC0OUT = 11, PWM cycle boundary is 0~15. B0BSET FTC0OUT Version 0.7 SONiX TECHNOLOGY CO., LTD Page 95... -
Page 96: Tc0 Timer Notice
Note: TC0C and TC0R can’t be set as 0xFF when TC0 timer operating in interrupt, buzzer output modes. TC0C and TC0R available range is 0x00~0xFE. The problem doesn’t exist in pure PWM mode. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 96... -
Page 97: Timer/Counter 1 (Tc1)
Auto. Reload TC1 / 2 P5.3 TC1R Reload Data Buffer PWM1OUT TC1 Rate Compare (Fcpu/2~Fcpu/256) TC1CKS TC1ENB Load Fcpu TC1C 8-Bit Binary Up TC1 Time Out Counting Counter INT1 (Schmitter Trigger) CPUM0,1 Version 0.7 SONiX TECHNOLOGY CO., LTD Page 97... -
Page 98: Tc1M Mode Register
0 = Disable TC1 timer. 1 = Enable TC1 timer. Note: When TC1CKS=1, TC1 became an external event counter and TC1RATE is useless. No more P0.1 interrupt request will be raised. (P0.1IRQ will be always 0). Version 0.7 SONiX TECHNOLOGY CO., LTD Page 98... -
Page 99: Tc1C Counting Register
Note: TC1C and TC1R can’t be set as 0xFF when TC1 timer operating in interrupt, buzzer output modes. TC1C and TC1R available range is 0x00~0xFE. The problem doesn’t exist in pure PWM mode. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 99... -
Page 100: Tc1R Auto-Load Register
= 100 = 64H Note: TC1R can’t be set as 0xFF when TC1 timer operating in interrupt, buzzer output modes. TC1R available range is 0x00~0xFE. The problem doesn’t exist in pure PWM mode. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 100... -
Page 101: Tc1 Clock Frequency Output (Buzzer)
; Enable TC1 output to P5.3 and disable P5.3 I/O function B0BSET FALOAD1 ; Enable TC1 auto-reload function B0BSET FTC1ENB ; Enable TC1 timer Note: Buzzer output is enabled, and “PWM1OUT” must be “0”. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 101... -
Page 102: Tc1 Timer Operation Sequence
; ALOAD1, TC1OUT = 01, PWM cycle boundary is 0~63. B0BSET FTC1OUT B0BSET FALOAD1 ; ALOAD1, TC1OUT = 10, PWM cycle boundary is 0~31. B0BCLR FTC1OUT B0BSET FALOAD1 ; ALOAD1, TC1OUT = 11, PWM cycle boundary is 0~15. B0BSET FTC1OUT Version 0.7 SONiX TECHNOLOGY CO., LTD Page 102... -
Page 103: Tc1 Timer Notice
Note: TC1C and TC1R can’t be set as 0xFF when TC1 timer operating in interrupt, buzzer output modes. TC1C and TC1R available range is 0x00~0xFE. The problem doesn’t exist in pure PWM mode. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 103... -
Page 104: Pwm0 Mode
125K Overflow per 16 count The Output duty of PWM is with different TC0R. Duty range is from 0/256~255/256. …… …… …… …… TC0 Clock TC0R=00H High TC0R=01H High TC0R=80H High TC0R=FFH Version 0.7 SONiX TECHNOLOGY CO., LTD Page 104... -
Page 105: Tc0Irq And Pwm Duty
PWM duty. TC0 Overflow, TC0IRQ = 1 0xFF TC0C Value 0x00 PWM0 Output (Duty Range 0~255) PWM0 Output (Duty Range 0~63) PWM0 Output (Duty Range 0~31) PWM0 Output (Duty Range 0~15) Version 0.7 SONiX TECHNOLOGY CO., LTD Page 105... -
Page 106: Pwm Program Example
TC0R, A INCMS BUF0 ; Get the new TC0R value from the BUF0 buffer defined by ; programming. B0MOV A, BUF0 B0MOV TC0R, A Note: The PWM can work with interrupt request. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 106... -
Page 107: Pwm0 Duty Changing Notice
Note: TC0C and TC0R can be 0xFF in pure PWM output. If PWM function is operating with TC0 interrupt, TC0C and TC0R can’t be set as 0xFF and the available range is 0x00~0xFE. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 107... - Page 108 … B0BTS1 FTC0IRQ INT_SER90 B0MOV A, TC0RBUF ; When TC0 Interrupt occurs, update TC0R. B0MOV TC0R, A … … INT_SER90: … ; Pop routine to load ACC and PFLAG from buffers. RETI Version 0.7 SONiX TECHNOLOGY CO., LTD Page 108...
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Page 109: Pwm1 Mode
125K Overflow per 16 count The Output duty of PWM is with different TC1R. Duty range is from 0/256~255/256. …… …… …… …… TC1 Clock TC1R=00H High TC1R=01H High TC1R=80H High TC1R=FFH Version 0.7 SONiX TECHNOLOGY CO., LTD Page 109... -
Page 110: Tc1Irq And Pwm Duty
PWM duty. TC1 Overflow, TC1IRQ = 1 0xFF TC1C Value 0x00 PWM1 Output (Duty Range 0~255) PWM1 Output (Duty Range 0~63) PWM1 Output (Duty Range 0~31) PWM1 Output (Duty Range 0~15) Version 0.7 SONiX TECHNOLOGY CO., LTD Page 110... -
Page 111: Pwm Program Example
TC1R, A INCMS BUF0 ; Get the new TC1R value from the BUF0 buffer defined by ; programming. B0MOV A, BUF0 B0MOV TC1R, A Note: The PWM can work with interrupt request. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 111... -
Page 112: Pwm1 Duty Changing Notice
Note: TC1C and TC1R can be 0xFF in pure PWM output. If PWM function is operating with TC1 interrupt, TC1C and TC1R can’t be set as 0xFF and the available range is 0x00~0xFE. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 112... - Page 113 … B0BTS1 FTC1IRQ INT_SER90 B0MOV A, TC1RBUF ; When TC1 Interrupt occurs, update TC1R. B0MOV TC1R, A … … INT_SER90: … ; Pop routine to load ACC and PFLAG from buffers. RETI Version 0.7 SONiX TECHNOLOGY CO., LTD Page 113...
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Page 114: Serial Input/Output Transceiver (Sio)
SIO clock idle status. CPHA bit is designed to control the clock edge direction of data receive. CPOL and CPHA bits decide the SIO format. The SIO data transfer direction is controlled by MLSB bit to decide MSB first or LSB first. SIO Interface Circuit Diagram Version 0.7 SONiX TECHNOLOGY CO., LTD Page 114... - Page 115 The transfer first bit = LSB. SCK data transfer edge = Rising edge. SCK idle status = High. The transfer first bit = LSB. SCK data transfer edge = Falling edge. SIO Data Transfer Timing Version 0.7 SONiX TECHNOLOGY CO., LTD Page 115...
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Page 116: Siom Mode Register
CPHA: The Clock Phase bit controls the phase of the clock on which data is sampled. 0 = Data receive at the first clock phase. 1 = Data receive at the second clock phase. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 116... -
Page 117: Siob Data Buffer
(SCKMD = 1) Read SIOB Read SIOB 2nd Receive Buffer 2nd Receive Buffer (Address = SIOB) (Address = SIOB) Write SIOB Write SIOB Shift Register Shift Register (SIOB) (SIOB) SIO Data Transfer Diagram Version 0.7 SONiX TECHNOLOGY CO., LTD Page 117... -
Page 118: Sior Register Description
Example: Setup the SIO clock to be 5KHz. Fosc = 3.58MHz. SIO’s rate = Fcpu = Fosc/4. SIOR = 256 – (1/(5KHz) * 3.58MHz/4) = 256 – (0.0002*895000) = 256 – 179 = 77 Version 0.7 SONiX TECHNOLOGY CO., LTD Page 118... -
Page 119: Main Serial Port (Msp)
0 = Start bit was not detected. 1 = Indicates that a start bit has been detected last Note1. It will be cleared when STOP bit was detected. Bit 2 RED_WRT: Read/Write bit information. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 119... -
Page 120: Msp Mode Register 1
Note1. After MSP Disable or Enable,must delay 2 instruction cycle. Ex: b0bset FMSPENB ..Ex:b0bclr FMSPENB …. Note2.MSP status register will be clear after MSP Disable. So,user should setting MSP register again befort MSP Enable. Ex:Call MSP_init_setting B0bset FMSPENB Version 0.7 SONiX TECHNOLOGY CO., LTD Page 120... -
Page 121: Msp Mode Register 2
0 = General call address disabled 1 = Enable interrupt when a general call address (0000h) is received. Bit 6 ACKSTAT: Acknowledge Status bit (In master mode only) In master transmit mode: Version 0.7 SONiX TECHNOLOGY CO., LTD Page 121... -
Page 122: Msp Mspbuf Register
Bit 2 Bit 1 Bit 0 MSPADR MSPADR7 MSPADR6 MSPADR5 MSPADR4 MSPADR3 MSPADR2 MSPADR1 MSPADR0 Read/Write After reset Bit [7:1] 7-bit Address. Bit 0 Tx/Rx mode control bit. 0=Tx mode. 1=Rx mode. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 122... -
Page 123: Slave Mode Operation
4. MSP interrupt request MSPIRQ is set on the falling edge of ninth SCL pulse. Status when Data is Received Reply an ACK MSPSP signal MSPIRQ MSPBUF MSPOV Data Received Action Table Note1. BF=0, MSPOV=1 shows the software is not set properly to clear Overflow register. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 123... -
Page 124: Slave Receiving
When overflow occur, no acknowledge signal replied which either BF=1 or MSPOV=1. MSP interrupt is generated in every data transfer. The MSPIRQ bit must be clear by software. Following is the Slave Receiving Diagram SLRXCKP=0 SLRXCKP=1 Version 0.7 SONiX TECHNOLOGY CO., LTD Page 124... -
Page 125: Slave Transmission
ACK_ = high, transmission is complete. Slave device will reset logic and waiting another START signal. If ACK_= low, slave must load MSPBUF which also MSPSR, and set CKP=1 to start data transmission again. MSP Slave Transmission Timing Diagram Version 0.7 SONiX TECHNOLOGY CO., LTD Page 125... -
Page 126: General Call Address
(ACK_) MSPIRQ flag set for interrupt request. In the interrupt service routine, reading MSPBUF can check if the address is the general call address or device specific. General Call Address Timing Diagram Version 0.7 SONiX TECHNOLOGY CO., LTD Page 126... -
Page 127: Slave Wake Up
Normal mode before Master sent START signal. Note:2. In MSP wake-up, if the address not match, MCU will keep in power down mode. Note 3. Clear MSPWK before enter power down mode by Software for wake-up indication. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 127... -
Page 128: Master Mode
MRG will reload when SCL pin is detected High. SCL clock rate = Fcpu/(MSPADDR)*2 For example, if we want to set 400Khz in 4Mhz Fcpu, the MSPADDR have to set 0x05h. MSPADDR=4Mhz/400Khz*2=5 MSP Rate Generator Block Diagram Version 0.7 SONiX TECHNOLOGY CO., LTD Page 128... -
Page 129: Msp Mater Start Condition
WCOL Status Flag If user write to MSPBUF when START condition processing, then WCOL is set and the content of MSPBUF data is un-changed. (the writer doesn’t occur) START Condition Timing Diagram Version 0.7 SONiX TECHNOLOGY CO., LTD Page 129... -
Page 130: Msp Master Mode Repeat Start Condition
WCOL Status Flag If user write to MSPBUF when Repeat START condition processing, then WCOL is set and the content of MSPBUF data is un-changed. (the writer doesn’t occur) Repeat Start Condition Timing Diagram Version 0.7 SONiX TECHNOLOGY CO., LTD Page 130... -
Page 131: Acknowledge Sequence Timing
Write ACKEN=1, ACKNDT=0 ACK_ MSPIRQ Clear MSPIRQ Clear MSPIRQ Set MSPIRQ at by Software by Software the end of receive Set MSPIRQ at the end of Acknowledge sequence Acknowledge Sequence Timing Diagram Version 0.7 SONiX TECHNOLOGY CO., LTD Page 131... -
Page 132: Stop Condition Timing
MSPADDR[6:0], and start down counter. This ensure that SCL high time will always be at least one MRG overflow time in the event that the clock is held low by an external device. Clock Arbitration sequence Timing Diagram Version 0.7 SONiX TECHNOLOGY CO., LTD Page 132... -
Page 133: Master Mode Transmission
(ACK_=1). A slave send an acknowledge when it has recognized its address (including general call), or when the slave has properly received the data. MSP Master Transmission Mode Timing Diagram Version 0.7 SONiX TECHNOLOGY CO., LTD Page 133... -
Page 134: Master Mode Receiving
WCOL Flag If user write to MSPBUF when a receive is already progress, the WCOL bit is set and the content of MSPBUF data will unchanged. MSP Master Receiving Mode Timing Diagram Version 0.7 SONiX TECHNOLOGY CO., LTD Page 134... -
Page 135: Channel Analog To Digital Converter
For 12-bit resolution the conversion time is 16 steps Note: The analog input level must be between the AVREFH and AVREFL. Note: The AVREFL connects to VSS internally in SN8P2754, SN8P2755 and SN8P2756. Note: The AVREFH level must be between the AVDD and AVREFL + 2.0V. -
Page 136: Adm Register
100 = AIN4, 101 = AIN5, 110 = AIN6, 111 = AIN7 Note: If ADENB = 1, users should set P4.n/AINn as input mode without pull-up. System doesn’t set automatically. If P4CON.n is set, the P4.n/AINn’s digital I/O function including pull-up is isolated. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 136... -
Page 137: Adr Registers
0 = 8-bit 1 = 12-bit. Bit [3:0] ADB [3:0]: ADC data buffer. ADB11~ADB4 bits for 8-bit ADC ADB11~ADB0 bits for 12-bit ADC Note: ADC buffer ADR [3:0] initial value after reset is unknown. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 137... -
Page 138: Adb Registers
ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADB3 ADB2 ADB1 ADB0 8-bit 9-bit 10-bit 11-bit 12-bit O = Selected, x = Delete Note: ADC buffer ADB initial value after reset is unknown. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 138... -
Page 139: P4Con Registers
1/(4MHz/8/4)*16 = 128 us 1 (12-bit) Fcpu 1/(4MHz/4)*16 = 16 us Fcpu/2 1/(4MHz/2/4)*16 = 32 us Fcpu/64 1/(4MHz/64/4)*16 = 1024 us Fcpu/32 1/(4MHz/32/4)*16 = 512 us 1 (12-bit) Fcpu/4 1/(4MHz/4/4)*16 = 64 us Reserved Reserved Version 0.7 SONiX TECHNOLOGY CO., LTD Page 139... -
Page 140: Adc Routine Example
Adc_Buf_Hi, A B0MOV A,ADR ; To get AIN0 input data bit3 ~ bit0 A, 0Fh B0MOV Adc_Buf_Low, A Power_Down B0BCLR FADENB ; Disable ADC circuit B0BCLR FCPUM1 B0BSET FCPUM0 ; Enter sleep mode Version 0.7 SONiX TECHNOLOGY CO., LTD Page 140... -
Page 141: Adc Circuit
Analog Signal Input 0.1uF VREFH Reference High Voltage Input 47uF 0.1uF ADC reference high voltage is from external voltage. The capacitor (47uF) between VREFH and VSS is necessary to stable VERFH voltage. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 141... -
Page 142: Digital To Analog Converter
1:The D/A converter is not designed for a precise DC voltage output and is suitable for a simple audio application e.g. Tone or Melody generation. 2:For best linearity performance, the max. Loading Resistance R is 150 ohm @5V, 100 ohm @3V Version 0.7 SONiX TECHNOLOGY CO., LTD Page 142... -
Page 143: Dam Register
DAB6 DAB5 DAB4 DAB3 DAB2 DAB1 DAB0 Idac 2 * Idac 3 * Idac 126 * Idac 127 * Idac Note: Idac = I / (2 -1) (I : Full-scale Output Current). Version 0.7 SONiX TECHNOLOGY CO., LTD Page 143... -
Page 144: Instruction Table
Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1. 2. If branch condition is true then “S = 1”, otherwise “S = 0”. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 144... -
Page 145: Electrical Characteristic
Ready to start convert after set ADENB = “1” VDD=5.0V ADCLK ADC Clock Frequency VDD=3.0V ADC Conversion Cycle Time VDD=2.4V~5.5V ADCYL ADCLK ADC Sampling Rate VDD=5.0V K/sec ADSMP (Set FADS=1 Frequency) VDD=3.0V K/sec Version 0.7 SONiX TECHNOLOGY CO., LTD Page 145... -
Page 146: Application Notice
SN8ICE 2K Plus: Full function emulates SN8P275X series. Use ICE emulation MSP function: 1. P10 must connect to LCD_CLK,P11 must connect to LCD_SDA. 2. P10/P11 is built-in open-drain function. When enable open-drain function, P10/P11 must connect pull-up resistor. Version 0.7 SONiX TECHNOLOGY CO., LTD Page 146... -
Page 147: Otp Writer
MPIII Writer: It's convenient to connect Full Speed USB 1.1 port with PC and then update the writer, connect programming chip or download programming code. 15.1.3 IDE (Integrated Development Environment) SONiX 8-bit MCU integrated development environment include Assembler, ICE debugger and OTP writer software. For SN8ICE 2K Plus: M2IDE V1.19 or later Version 0.7 SONiX TECHNOLOGY CO., LTD... -
Page 148: Otp Programming Pin
13 D7 D6 13 14 D7 VPP 16 15 VDD VPP 15 16 VDD RST 18 17 HLS RST 17 18 HLS Writer V2.5 JP1 Pin Assignment Writer V3.0 JP1 Pin Assignment Version 0.7 SONiX TECHNOLOGY CO., LTD Page 148... -
Page 149: Sn8P275X Series Programming Pin Mapping
OTP IC / JP3 Pin Assignment V3.0 Number Number Number Number 3,14,24 4,26 8,16,36,37 7,21 1,16 5,25 P5.0 P5.0 P5.0 P1.0 P1.0 P1.0 P5.1 P5.1 P5.1 3,14,24 4,26 8,16,36,37 ALSB/PDB 5,22 P1.1/P3.1 13,2 P1.1/P3.1 19,6 P1.1/P3.1 Version 0.7 SONiX TECHNOLOGY CO., LTD Page 149... -
Page 150: Package Information
PACKAGE INFORMATION 16.1 SK-DIP28 PIN Symbols MIN. NOR. MAX. 0.210 0.015 0.114 0.130 0.135 1.390 1.390 1.400 0.310BSC. 0.283 0.288 0.293 0.115 0.130 0.150 ｅ 0.330 0.350 0.370 θ ° UNIT : INCH Version 0.7 SONiX TECHNOLOGY CO., LTD Page 150... -
Page 151: Sop28 Pin
SN8P275X Series 8-bit micro-controller build-in 12-bit ADC 16.2 SOP28 PIN Symbols MIN. MAX. 0.093 0.104 0.004 0.012 0.697 0.713 0.291 0.299 0.394 0.419 0.016 0.050 θ ° UNIT : INCH Version 0.7 SONiX TECHNOLOGY CO., LTD Page 151... -
Page 152: P-Dip 32 Pin
SN8P275X Series 8-bit micro-controller build-in 12-bit ADC 16.3 P-DIP 32 PIN 16.4 SOP 32 PIN Version 0.7 SONiX TECHNOLOGY CO., LTD Page 152... -
Page 153: Ssop 48 Pin
15.748 15.875 16.002 0.291 0.295 0.299 7.391 7.493 7.595 0.025 0.635 0.396 0.406 0.416 10.058 10.312 10.566 0.020 0.030 0.040 0.508 0.762 1.016 0.056 1.422 0.003 0.076 θ° 0° 8° 0° 8° Version 0.7 SONiX TECHNOLOGY CO., LTD Page 153... -
Page 154: Lqfp 48 Pin
8-bit micro-controller build-in 12-bit ADC 16.6 LQFP 48 PIN SYMBOLS (mm) 0.05 0.15 1.35 1.45 0.09 0.16 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.5 BSC 0.17 0.27 0.45 0.75 1 REF Version 0.7 SONiX TECHNOLOGY CO., LTD Page 154... -
Page 155: Marking Definition
Marking Definition 17.1 INTRODUCTION There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit MCU for order or obtain information. This definition is only for Blank OTP MCU. 17.2 MARKING INDETIFICATION SYSTEM SN8 X PART No. -
Page 156: Marking Example
..9=09 A=10 B=11 ..1=January Month 2=February ..9=September A=October B=November C=December 03= 2003 Year 04= 2004 05= 2005 06= 2006 ..Version 0.7 SONiX TECHNOLOGY CO., LTD Page 156... - Page 157 SONIX product could create a situation where personal injury or death may occur.
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