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SN8PC20
USER'S MANUAL
Version 0.9
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
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Page 1
Remote Control 8-Bit Micro-Controller
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Version 0.9
SN8PC20
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Summary of Contents for SONIX SN8PC20
- Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.
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Page 2: Amendent History
℃ to -20~70℃. 1. Modify “ELECTRICAL CHARACTERISTIC” Supply voltage VER 0.8 Dec. 2014 1. Modify “IR APPLICATION CIRCUIT“ section. VER 0.9 May 2018 2. Modify ” ICE and EV-KIT APPLICATION NOTIC” section. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 2... -
Page 3: Table Of Contents
LOW VOLTAGE DETECTOR (LVD) ................... 38 3.4.3 BROWN OUT RESET IMPROVEMENT................39 EXTERNAL RESET ........................40 EXTERNAL RESET CIRCUIT ....................... 40 3.6.1 Simply RC Reset Circuit ......................40 3.6.2 Diode & RC Reset Circuit ......................41 Version 0.9 SONiX TECHNOLOGY CO., LTD Page 3... - Page 4 T0M MODE REGISTER ......................69 8.2.4 T0C COUNTING REGISTER ....................69 8.2.5 T0 TIMER OPERATION SEQUENCE ................... 70 IR OUTPUT ............................71 OVERVIEW ............................. 71 IR CONTROL REGISTER ....................... 71 9.2.1 IRM MODE REGISTER ......................71 Version 0.9 SONiX TECHNOLOGY CO., LTD Page 4...
- Page 5 PACKAGE INFORMATION ......................85 15.1 P-DIP 20 PIN ............................ 85 15.2 SOP 20 PIN ............................86 15.3 SSOP 20 PIN ............................. 87 15.4 SOP 16 PIN ............................88 15.5 SOP 14 PIN ............................89 Version 0.9 SONiX TECHNOLOGY CO., LTD Page 5...
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Page 6: Product Overview
Duty/cycle programmable, PDIP20/SOP20/ SN8PC13 2K*16 Normal current SSOP20 Duty/cycle programmable, PDIP20/SOP20/ SN8PC20 2K*16 400mA sink current SSOP20 Duty/cycle programmable, SN8PC2016 2K*16 SOP16 400mA sink current Duty/cycle programmable, SN8PC2014 2K*16 SOP14 400mA sink current Version 0.9 SONiX TECHNOLOGY CO., LTD Page 6... -
Page 7: System Block Diagram
1.2 SYSTEM BLOCK DIAGRAM INTERNAL HIGH RC 8MHz 1-Level LVD EXTERNAL INTERNAL (Low Voltage Detector) HIGH OSC. LOW RC FLAGS TIMING GENERATOR WATCHDOG TIMER IR Generator IR Output SYSTEM REGISTERS INTERRUPT CONTROL TIMER & COUNTER Version 0.9 SONiX TECHNOLOGY CO., LTD Page 7... -
Page 8: Pin Assignment
SN8PC2016S (SOP 16 pins) P0.0/INT0 P5.4/IROUT P0.1 P5.0 P0.2/RST/VPP P1.5 P0.3/XIN P1.4 P0.4/XOUT P1.3 P0.5 P1.2 P1.0 P1.1 SN8PC2014S (SOP 14 pins) P0.0/INT0 P5.4/IROUT P0.1 P5.0 P0.2/RST/VPP P1.3 P0.3/XIN P1.2 P0.4/XOUT P1.1 P0.5 P1.0 Version 0.9 SONiX TECHNOLOGY CO., LTD Page 8... -
Page 9: Pin Descriptions
P5.0: Bi-direction pin. Schmitt trigger structure. Built-in pull-up resistors as input mode. P5.4: Bi-direction pin. Schmitt trigger structure. Built-in pull-up resistors as input mode. P5.4/IROUT IROUT: Duty/cycle programmable IR signal output pin. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 9... -
Page 10: Pin Circuit Diagrams
Code Option Input Bus Output Output Bus Latch Oscillator IR output shared I/O with Schmitt-trigger (ViH=0.7*Vdd, ViL=0.3*Vdd) and Pull-up Resistor(200KΩ@3V): Pull-Up Resistor PnUR IREN Input Bus Output Output Bus Latch IR Signal Version 0.9 SONiX TECHNOLOGY CO., LTD Page 10... -
Page 11: Central Processor Unit (Cpu)
The Interrupt vector is the head of interrupt service routine when any interrupt occurring. The General purpose area is main program area including main loop, sub-routines and data table. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 11... -
Page 12: Reset Vector (0000H)
Example: Defining Reset Vector ; 0000H START ; Jump to user program address. … START: ; 0010H, The head of user program. … ; User program … ENDP ; End of program Version 0.9 SONiX TECHNOLOGY CO., LTD Page 12... -
Page 13: Interrupt Vector (0008H)
RETI ; End of interrupt service routine … START: ; The head of user program. … ; User program … START ; End of user program … ENDP ; End of program Version 0.9 SONiX TECHNOLOGY CO., LTD Page 13... - Page 14 ; End of program. Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
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Page 15: Look-Up Table Description
Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Example: INC_YZ macro. INC_YZ MACRO INCMS ; Z+1 ; Not overflow INCMS ; Y+1 ; Not overflow ENDM Version 0.9 SONiX TECHNOLOGY CO., LTD Page 15... - Page 16 ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 … TABLE1: 0035H ; To define a word (16 bits) data. 5105H 2012H … Version 0.9 SONiX TECHNOLOGY CO., LTD Page 16...
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Page 17: Jump Table Description
; ACC = 3, jump to A3POINT SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size. - Page 18 ; ACC = 1, jump to A1POINT 0X0102 A2POINT ; ACC = 2, jump to A2POINT 0X0103 A3POINT ; ACC = 3, jump to A3POINT 0X0104 A4POINT ; ACC = 4, jump to A4POINT Version 0.9 SONiX TECHNOLOGY CO., LTD Page 18...
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Page 19: Checksum Calculation
; If Not jump to checksum calculate CHECKSUM_END ; If Yes checksum calculated is done. Y_ADD_1: INCMS ; Increase Y ; Jump to checksum calculate CHECKSUM_END: … … END_USER_CODE: ; Label of program end Version 0.9 SONiX TECHNOLOGY CO., LTD Page 19... -
Page 20: Data Memory (Ram)
(128 bytes). “ System Register “ 0FFh End of Bank 0 Sonix provides “Bank 0” type instructions (e.g. b0mov, b0add, b0bts1, b0bset…) to control Bank 0 RAM directly. 2.2.1 SYSTEM REGISTER 2.2.1.1 SYSTEM REGISTER TABLE PFLAG PEDGE INTRQ INTEN OSCM... -
Page 21: Bit Definition Of System Register
All of register names had been declared in SN8ASM assembler. One-bit name had been declared in SN8ASM assembler with “F” prefix code. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 21... -
Page 22: Accumulator
“PUSH”, “POP” save and load ACC, PFLAG data into buffers. Example: Protect ACC and working registers. INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector Version 0.9 SONiX TECHNOLOGY CO., LTD Page 22... -
Page 23: Program Flag
1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero. Note: Refer to instruction set table for detailed information of C, DC and Z flags. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 23... -
Page 24: Program Counter
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. CMPRS A, #12H ; To skip, if ACC = 12H. C0STEP ; Else jump to C0STEP. … … C0STEP: Version 0.9 SONiX TECHNOLOGY CO., LTD Page 24... - Page 25 DECS BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: DECMS instruction: DECMS BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: Version 0.9 SONiX TECHNOLOGY CO., LTD Page 25...
- Page 26 ; If ACC = 0, jump to A0POINT A1POINT ; ACC = 1, jump to A1POINT A2POINT ; ACC = 2, jump to A2POINT A3POINT ; ACC = 3, jump to A3POINT … … Version 0.9 SONiX TECHNOLOGY CO., LTD Page 26...
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Page 27: H, L Registers
; Clear @HL to be zero ; L – 1, if L = 0, finish the routine DECMS CLR_HL_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … … Version 0.9 SONiX TECHNOLOGY CO., LTD Page 27... -
Page 28: Y, Z Registers
; Clear @YZ to be zero ; Z – 1, if Z= 0, finish the routine DECMS CLR_YZ_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … Version 0.9 SONiX TECHNOLOGY CO., LTD Page 28... -
Page 29: R Register
Bit 2 Bit 1 Bit 0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Read/Write After reset Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 29... -
Page 30: Addressing Mode
; To clear Y register to access RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 30... -
Page 31: Stack Operation
High Byte Low Byte STKP = 3 STK3H STK3L STKP + 1 STKP - 1 STKP = 2 STK2H STK2L STKP = 1 STK1H STK1L STKP STKP STKP = 0 STK0H STK0L Version 0.9 SONiX TECHNOLOGY CO., LTD Page 31... -
Page 32: Stack Registers
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKnL SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0 Read/Write After reset STKn = STKnH , STKnL (n = 3 ~ 0) Version 0.9 SONiX TECHNOLOGY CO., LTD Page 32... -
Page 33: Stack Operation Example
(PC) to the program counter registers. The Stack-Restore operation is as the following table. STKP Register Stack Buffer Stack Level Description STKPB1 STKPB0 High Byte Low Byte STK3H STK3L STK2H STK2L STK1H STK1L STK0H STK0L Free Free Version 0.9 SONiX TECHNOLOGY CO., LTD Page 33... -
Page 34: Code Option Table
P02: Set reset pin to general input only pin (P0.2). The external reset function is disabled and the pin is input pin. 2.5.2 Security code option Security code option is OTP ROM protection. When enable security code option, the ROM code is secured and not dumped complete ROM contents. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 34... -
Page 35: Reset
High Detect Low Detect Watchdog Overflow Watchdog Normal Run Watchdog Reset Watchdog Stop System Normal Run System Status System Stop Power On External Watchdog Delay Time Reset Delay Reset Delay Time Time Version 0.9 SONiX TECHNOLOGY CO., LTD Page 35... -
Page 36: Power On Reset
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the watchdog timer function. Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 36... -
Page 37: Brown Out Reset
DC low battery condition. When turn off the AC power, the VDD drops slowly and through the dead-band for a while. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 37... -
Page 38: The System Operating Voltage
Delay Time The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by each MCU. -
Page 39: Brown Out Reset Improvement
IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead-band. The external reset information is described in the next section. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 39... -
Page 40: External Reset
The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference. Note: The reset circuit is no any protection against unusual power or brown out reset. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 40... -
Page 41: Diode & Rc Reset Circuit
PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener specification. Select the right zener voltage to conform the application. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 41... -
Page 42: Voltage Bias Reset Circuit
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can improve all power variation. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 42... -
Page 43: System Clock
4MHz/4 = 1MHz. Under system slow mode, the Fcpu is fixed Flosc/4, 10KHz/4=2.5KHz @3V. In high noisy environment, below “Fhosc/4” of Fcpu code option is the strongly recommendation to reduce high frequency noise effect. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 43... -
Page 44: System High-Speed Clock
455KHz crystal/ceramic and RC type. These high-speed oscillators are selected by “High_CLK” code option. 4.3.1 HIGH_CLK CODE OPTION For difference clock functions, Sonix provides multi-type system high clock options controlled by “High_CLK” code option. The High_CLK code option defines the system oscillator types including IHRC_8M, RC, 455K X’tal, 8M X’tal and 4M X’tal. -
Page 45: External Oscillator Application Circuit
Note: Connect the Crystal/Ceramic and C as near as possible to the XIN/XOUT/VSS pins of micro-controller. Connect the R and C as near as possible to the VDD pin of micro-controller. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 45... -
Page 46: System Low-Speed Clock
; oscillator called power down mode (sleep mode). Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1 (455K, watchdog disable) bits of OSCM register. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 46... -
Page 47: Oscm Register
; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P0.0 ; Measure the Fcpu frequency by oscilloscope. Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC frequency. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 47... -
Page 48: System Clock Timing
External Reset Flag Oscillator Tcfg Tost Tosp Fcpu (Instruction Cycle) System is under reset status. Watchdog Reset Timing Watchdog timer overflow. Watchdog Reset Flag Oscillator Tcfg Tost Tosp Fcpu (Instruction Cycle) Version 0.9 SONiX TECHNOLOGY CO., LTD Page 48... - Page 49 The RC type oscillator’s start-up time is faster than crystal type oscillator. External RC Tost Ceramic/Resonator Tost Crystal Tost Low Speed Crystal (32K, 455K) Tost Version 0.9 SONiX TECHNOLOGY CO., LTD Page 49...
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Page 50: System Operation Mode
All active All inactive Wakeup source P0, P1, T0, Reset P0, P1, Reset EHOSC: External high-speed oscillator (XIN/XOUT). IHRC: Internal high-speed oscillator RC type. ILRC: Internal low-speed oscillator RC type. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 50... -
Page 51: Normal Mode
Note: If the system is in normal mode, to set STPHX=1 to disable the high clock oscillator. The system is under no system clock condition. This condition makes the system stay as power down mode, and can be wake-up by P0, P1 level change trigger. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 51... -
Page 52: Green Mode
PWN and buzzer output functions active in green mode, but the timer can’t wake-up the system as overflow. Note: Sonix provides “GreenMode” macro to control green mode operation. It is necessary to use “GreenMode” macro to control system inserting green mode. -
Page 53: Operating Mode Control Macro
SN8PC20 Remote Control 8-Bit Micro-Controller OPERATING MODE CONTROL MACRO Sonix provides operating mode control macros to switch system operating mode easily. Macro Length Description SleepMode 1-word The system insets into Sleep Mode (Power Down Mode). GreenMode 3-word The system inserts into Green Mode. -
Page 54: Wakeup
The wakeup time is as the following. The wakeup time = 1/Fosc * 2048 = 0.512 ms (Fosc = 4MHz) The total wakeup time = 0.512 ms + oscillator start-up time Version 0.9 SONiX TECHNOLOGY CO., LTD Page 54... -
Page 55: P1W Wakeup Control Register
Bit 0 P17W P16W P15W P14W P13W P12W P11W P10W Read/Write After reset Bit[7:0] P10W~P17W: Port 1 wakeup function control bits. 0 = Disable P1n wakeup function. 1 = Enable P1n wakeup function. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 55... -
Page 56: Interrupt
0 = Disable INT0 interrupt function. 1 = Enable INT0 interrupt function. Bit 4 T0IEN: T0 timer interrupt control bit. 0 = Disable T0 interrupt function. 1 = Enable T0 interrupt function. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 56... -
Page 57: Intrq Interrupt Request Register
0 = Disable global interrupt. 1 = Enable global interrupt. Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE Note: The GIE bit must enable during all interrupt operation. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 57... -
Page 58: Push, Pop Routine
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine executed. START INT_SERVICE START: … INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector … ENDP Version 0.9 SONiX TECHNOLOGY CO., LTD Page 58... -
Page 59: External Interrupt Operation (Int0)
; P00IRQ = 0, exit interrupt vector B0BCLR FP00IRQ ; Reset P00IRQ … ; INT0 interrupt service routine EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.9 SONiX TECHNOLOGY CO., LTD Page 59... -
Page 60: T0 Interrupt Operation
A, #74H B0MOV T0C, A ; Reset T0C. … ; T0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.9 SONiX TECHNOLOGY CO., LTD Page 60... -
Page 61: Multi-Interrupt Operation
; End of interrupt request checking B0BTS0 FT0IRQ ; Check T0IRQ INTT0 ; Jump to T0 interrupt service routine … INT_EXIT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.9 SONiX TECHNOLOGY CO., LTD Page 61... -
Page 62: I/O Port
High_CLK code option = 455K, 4M, 8M P0.3 High_CLK code option = RC, 455K, 4M, 8M P5.4 IROUT IREN = 1. * DC: Digital Characteristic. AC: Analog Characteristic. HV: High Voltage Characteristic. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 62... -
Page 63: I/O Port Mode
; Set all ports to be output mode. B0MOV P0M, A B0MOV P1M,A B0MOV P5M, A B0BCLR P1M.0 ; Set P1.0 to be input mode. B0BSET P1M.0 ; Set P1.0 to be output mode. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 63... -
Page 64: I/O Pull Up Register
Note: P0.2 is input only pin and without pull-up resister. The P0UR.2 is undefined. Example: I/O Pull up Register A, #0FFH ; Enable Port 0, 1, 5 Pull-up register, B0MOV P0UR, A B0MOV P1UR,A B0MOV P5UR, A Version 0.9 SONiX TECHNOLOGY CO., LTD Page 64... -
Page 65: I/O Port Data Register
Example: Write one bit data to output port. ; Set P1.0 and P5.3 to be “1”. B0BSET P1.0 B0BSET P5.3 ; Set P1.0 and P5.3 to be “0”. B0BCLR P1.0 B0BCLR P5.3 Version 0.9 SONiX TECHNOLOGY CO., LTD Page 65... -
Page 66: Timers
; Clear the watchdog timer. B0MOV WDTR, A … CALL SUB1 CALL SUB2 … MAIN Example: Clear watchdog timer by “@RST_WDT” macro of Sonix IDE. Main: @RST_WDT ; Clear the watchdog timer. … CALL SUB1 CALL SUB2 … MAIN Version 0.9... - Page 67 ; I/O and RAM are correct. Clear watchdog timer and ; execute program. A, #5AH ; Clear the watchdog timer. B0MOV WDTR, A … CALL SUB1 CALL SUB2 … … … MAIN Version 0.9 SONiX TECHNOLOGY CO., LTD Page 67...
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Page 68: Timer 0 (T0)
T0 counter doesn’t build in auto-reload function. Set the T0 interval time through setting T0C by program and have to set again when T0 timer overflows, or T0 timer counts from 0x00 to 0xFF 256 counts. Not keep the correct interval time. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 68... -
Page 69: T0M Mode Register
16 us 500 ms 1953.125 us Fcpu/8 2.048 ms 8 us 250 ms 976.563 us Fcpu/4 1.024 ms 4 us 125 ms 488.281 us Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us Version 0.9 SONiX TECHNOLOGY CO., LTD Page 69... -
Page 70: T0 Timer Operation Sequence
Set T0 interrupt interval time. A,#7FH B0MOV T0C,A ; Set T0C value. Set T0 timer function mode. B0BSET FT0IEN ; Enable T0 interrupt function. Enable T0 timer. B0BSET FT0ENB ; Enable T0 timer. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 70... -
Page 71: Ir Output
0 = Disable. IROUT pin is output high status. 1 = Enable. IROUT pin outputs IR carry signal. Note: IR carry output condition is IREN=1 and CREN=1. If CREN=1 and IREN=0, the IROUT pin is P5.4 GPIO mode. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 71... -
Page 72: Irc Counting Register
IRR initial value = 256 - (IR interrupt interval time * input clock) IR interval time = 1/38KHz = 26.3us Input clock = external oscillator 4MHz. IRR = 256 - (26.3us * 4MHz) = 150.8 ≈ 151 = 97h Version 0.9 SONiX TECHNOLOGY CO., LTD Page 72... -
Page 73: Ird Ir Duty Control Register
1/2 duty 1/3 duty 1/4duty (KHz) Rate 193.50 172.67 162.25 0.00% 200.50 182.00 172.75 0.10% 203.50 186.00 177.25 0.25% 39.2 205.00 188.00 179.50 0.04% 206.00 189.33 181.00 0.00% 220.50 208.67 202.75 0.60% Version 0.9 SONiX TECHNOLOGY CO., LTD Page 73... -
Page 74: Ir Output Operation Sequence
A, #IRDUTYVAL ;IRD value for IR duty. IRD, A Enable IR output. BSET FIREN ; Set IROUT pin to IR carry output function. BSET FCREN ; Set IR carry signal output. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 74... -
Page 75: Ir Application Circuit
KO7 KO8 IHRC_8M type, Max. 72 keys: R1 3.75 ohm P0.0 P5.4/IROUT P0.1 P5.0 47uF 0.1uF P0.2/RST P1.7 P0.3/XIN P1.6 P0.4/XOUT P1.5 P0.5 P1.4 47k ohm P0.6 P1.3 P0.7 P1.2 P1.0 P1.1 SN8PC20 Version 0.9 SONiX TECHNOLOGY CO., LTD Page 75... -
Page 76: Instruction Table
Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1. 2. If branch condition is true then “S = 1”, otherwise “S = 0”. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 76... -
Page 77: Electrical Characteristic
Internal High Oscillator Freq. Fihrc Internal Hihg RC (IHRC) Vdd= 3V, 7.84 8.16 Fcpu = 1MHz LVD Voltage Vdet0 Low voltage reset level. “ ” These parameters are for design reference, not tested. Version 0.9 SONiX TECHNOLOGY CO., LTD Page 77... -
Page 78: Characteristic Graphs
8.10 8.15 8.10 8.00 0℃ 8.05 10℃ VDD=3V 25℃ 8.00 7.90 50℃ 7.95 70℃ 7.80 7.90 7.85 7.70 7.80 7.60 7.75 2.0V 2.5V 3.0V 3.5V 4.0V VDD (V) Tem peture (℃ ) Version 0.9 SONiX TECHNOLOGY CO., LTD Page 78... -
Page 79: Development Tool
IDE: SONiX IDE M2IDE_V115. Writer: MPIII WRITER-LV. 12.1 SN8PC20 EV-KIT SN8PC20 EV-kit includes ICE interface , GPIO interface and IR driver module. The schematic of SN8PC20 EV-kit is as following. CON1: ICE interface connected to SN8ICE2K . ... -
Page 80: Ice And Ev-Kit Application Notic
SN8PC20 real chip test and disconnected with ICE. The EV-kit is like a real remote controller. If the SN8PC20 real chip is set as 455KHz oscillator mode, the C4 (XIN) capacitance must be 47pF and C5 (XOUT) capacitance must be 20pF. -
Page 81: Otp Programming Pin
JP1 for MP transition board DIP12 DIP38 DIP13 DIP36 DIP14 DIP35 DIP15 DIP34 DIP16 DIP33 DIP17 DIP32 DIP18 DIP31 DIP19 DIP30 DIP20 DIP29 DIP21 DIP28 DIP22 DIP27 DIP23 DIP26 DIP24 DIP25 JP3 for MP transition board Version 0.9 SONiX TECHNOLOGY CO., LTD Page 81... -
Page 82: Programming Pin Mapping
SN8PC20 Remote Control 8-Bit Micro-Controller 13.2 PROGRAMMING PIN MAPPING: Programming Information of SN8PC20 Chip Name SN8PC20P/S/X SN8PC2016S SN8PC2014S EZ Writer OTP IC / JP3 Pin Assignment Connector Number Name Number Number Number P1.2 P1.2 P1.2 P1.0 P1.0 P1.0 P1.3 P1.3 P1.3... -
Page 83: Marking Definition
Marking Definition 14.1 INTRODUCTION There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit MCU for order or obtain information. This definition is only for Blank OTP MCU. 14.2 MARKING INDETIFICATION SYSTEM SN8 X Part No. -
Page 84: Marking Example
..9=09 A=10 B=11 ..1=January Month 2=February ..9=September A=October B=November C=December 03= 2003 Year 04= 2004 05= 2005 06= 2006 ..Version 0.9 SONiX TECHNOLOGY CO., LTD Page 84... -
Page 85: Package Information
1.060 24.892 26.162 26.924 0.300 7.620 0.245 0.250 0.255 6.223 6.350 6.477 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.335 0.355 0.375 8.509 9.017 9.525 θ° 0° 7° 15° 0° 7° 15° Version 0.9 SONiX TECHNOLOGY CO., LTD Page 85... -
Page 86: Sop 20 Pin
0.305 0.496 0.502 0.508 12.598 12.751 12.903 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.325 10.643 0.016 0.033 0.050 0.406 0.838 1.270 θ° 0° 4° 8° 0° 4° 8° Version 0.9 SONiX TECHNOLOGY CO., LTD Page 86... -
Page 87: Ssop 20 Pin
3.800 3.900 4.000 0.025 0.635 0.010 0.017 0.020 0.250 0.420 0.500 0.016 0.025 0.050 0.400 0.635 1.270 0.039 0.041 0.043 1.000 1.050 1.100 0.059 1.500 0.004 0.100 θ° 0° 8° 0° 8° Version 0.9 SONiX TECHNOLOGY CO., LTD Page 87... -
Page 88: Sop 16 Pin
SYMBOLS (inch) (mm) 0.053 0.069 1.346 1.753 0.004 0.010 0.102 0.254 0.386 0.394 9.804 10.008 0.150 0.157 3.810 3.988 0.228 0.244 5.791 6.198 0.016 0.050 0.406 1.270 θ° 0° 8° 0° 8° Version 0.9 SONiX TECHNOLOGY CO., LTD Page 88... -
Page 89: Sop 14 Pin
0.2490 0.336 0.341 0.344 8.5344 8.6614 8.7376 0.150 0.154 0.157 3.81 3.9116 3.9878 0.050 1.27 0.228 0.236 0.244 5.7912 5.9944 6.1976 0.015 0.025 0.050 0.381 0.635 1.27 θ° 0° 8° 0° 8° Version 0.9 SONiX TECHNOLOGY CO., LTD Page 89... - Page 90 SONIX product could create a situation where personal injury or death may occur.
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